blob: aaab9c9cebee6b57d0ac8ef0b9e8e4bd683ee541 [file] [log] [blame]
Hans Verkuil54450f52012-07-18 05:45:16 -03001/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
Laurent Pinchartc72a53c2014-01-30 19:18:34 -030030#include <linux/delay.h>
Laurent Pincharte9d50e92014-01-30 18:37:08 -030031#include <linux/gpio/consumer.h>
Laurent Pinchartc72a53c2014-01-30 19:18:34 -030032#include <linux/i2c.h>
Hans Verkuil54450f52012-07-18 05:45:16 -030033#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/slab.h>
Laurent Pinchartc72a53c2014-01-30 19:18:34 -030036#include <linux/v4l2-dv-timings.h>
Hans Verkuil54450f52012-07-18 05:45:16 -030037#include <linux/videodev2.h>
38#include <linux/workqueue.h>
Laurent Pinchartc72a53c2014-01-30 19:18:34 -030039
Hans Verkuil54450f52012-07-18 05:45:16 -030040#include <media/adv7604.h>
Laurent Pinchartc72a53c2014-01-30 19:18:34 -030041#include <media/v4l2-ctrls.h>
42#include <media/v4l2-device.h>
43#include <media/v4l2-dv-timings.h>
Laurent Pinchart6fa88042014-02-04 20:23:16 -030044#include <media/v4l2-of.h>
Hans Verkuil54450f52012-07-18 05:45:16 -030045
46static int debug;
47module_param(debug, int, 0644);
48MODULE_PARM_DESC(debug, "debug level (0-2)");
49
50MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
51MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
52MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
53MODULE_LICENSE("GPL");
54
55/* ADV7604 system clock frequency */
Pablo Antonb44b2e02015-02-03 14:13:18 -030056#define ADV76XX_FSC (28636360)
Hans Verkuil54450f52012-07-18 05:45:16 -030057
Pablo Antonb44b2e02015-02-03 14:13:18 -030058#define ADV76XX_RGB_OUT (1 << 1)
Laurent Pinchart539b33b2014-01-26 18:42:37 -030059
Pablo Antonb44b2e02015-02-03 14:13:18 -030060#define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
Laurent Pinchart539b33b2014-01-26 18:42:37 -030061#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
Pablo Antonb44b2e02015-02-03 14:13:18 -030062#define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
Laurent Pinchart539b33b2014-01-26 18:42:37 -030063
Pablo Antonb44b2e02015-02-03 14:13:18 -030064#define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
Laurent Pinchart539b33b2014-01-26 18:42:37 -030065#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
Pablo Antonb44b2e02015-02-03 14:13:18 -030066#define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
Laurent Pinchart539b33b2014-01-26 18:42:37 -030067#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
Pablo Antonb44b2e02015-02-03 14:13:18 -030068#define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
Laurent Pinchart539b33b2014-01-26 18:42:37 -030069#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
70
Pablo Antonb44b2e02015-02-03 14:13:18 -030071#define ADV76XX_OP_CH_SEL_GBR (0 << 5)
72#define ADV76XX_OP_CH_SEL_GRB (1 << 5)
73#define ADV76XX_OP_CH_SEL_BGR (2 << 5)
74#define ADV76XX_OP_CH_SEL_RGB (3 << 5)
75#define ADV76XX_OP_CH_SEL_BRG (4 << 5)
76#define ADV76XX_OP_CH_SEL_RBG (5 << 5)
Laurent Pinchart539b33b2014-01-26 18:42:37 -030077
Pablo Antonb44b2e02015-02-03 14:13:18 -030078#define ADV76XX_OP_SWAP_CB_CR (1 << 0)
Laurent Pinchart539b33b2014-01-26 18:42:37 -030079
Pablo Antonb44b2e02015-02-03 14:13:18 -030080enum adv76xx_type {
Lars-Peter Clausend42010a2013-11-25 15:45:07 -030081 ADV7604,
82 ADV7611,
83};
84
Pablo Antonb44b2e02015-02-03 14:13:18 -030085struct adv76xx_reg_seq {
Lars-Peter Clausend42010a2013-11-25 15:45:07 -030086 unsigned int reg;
87 u8 val;
88};
89
Pablo Antonb44b2e02015-02-03 14:13:18 -030090struct adv76xx_format_info {
Boris BREZILLONf5fe58f2014-11-10 14:28:29 -030091 u32 code;
Laurent Pinchart539b33b2014-01-26 18:42:37 -030092 u8 op_ch_sel;
93 bool rgb_out;
94 bool swap_cb_cr;
95 u8 op_format_sel;
96};
97
Pablo Antonb44b2e02015-02-03 14:13:18 -030098struct adv76xx_chip_info {
99 enum adv76xx_type type;
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300100
101 bool has_afe;
102 unsigned int max_port;
103 unsigned int num_dv_ports;
104
105 unsigned int edid_enable_reg;
106 unsigned int edid_status_reg;
107 unsigned int lcf_reg;
108
109 unsigned int cable_det_mask;
110 unsigned int tdms_lock_mask;
111 unsigned int fmt_change_digital_mask;
jean-michel.hautbois@vodalys.com80f49442015-02-04 11:16:00 -0300112 unsigned int cp_csc;
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300113
Pablo Antonb44b2e02015-02-03 14:13:18 -0300114 const struct adv76xx_format_info *formats;
Laurent Pinchart539b33b2014-01-26 18:42:37 -0300115 unsigned int nformats;
116
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300117 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
118 void (*setup_irqs)(struct v4l2_subdev *sd);
119 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
120 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
121
122 /* 0 = AFE, 1 = HDMI */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300123 const struct adv76xx_reg_seq *recommended_settings[2];
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300124 unsigned int num_recommended_settings[2];
125
126 unsigned long page_mask;
127};
128
Hans Verkuil54450f52012-07-18 05:45:16 -0300129/*
130 **********************************************************************
131 *
132 * Arrays with configuration parameters for the ADV7604
133 *
134 **********************************************************************
135 */
Laurent Pinchartc784b1e2014-01-29 10:08:58 -0300136
Pablo Antonb44b2e02015-02-03 14:13:18 -0300137struct adv76xx_state {
138 const struct adv76xx_chip_info *info;
139 struct adv76xx_platform_data pdata;
Laurent Pinchart539b33b2014-01-26 18:42:37 -0300140
Laurent Pincharte9d50e92014-01-30 18:37:08 -0300141 struct gpio_desc *hpd_gpio[4];
142
Hans Verkuil54450f52012-07-18 05:45:16 -0300143 struct v4l2_subdev sd;
Pablo Antonb44b2e02015-02-03 14:13:18 -0300144 struct media_pad pads[ADV76XX_PAD_MAX];
Laurent Pinchartc784b1e2014-01-29 10:08:58 -0300145 unsigned int source_pad;
Laurent Pinchart539b33b2014-01-26 18:42:37 -0300146
Hans Verkuil54450f52012-07-18 05:45:16 -0300147 struct v4l2_ctrl_handler hdl;
Laurent Pinchart539b33b2014-01-26 18:42:37 -0300148
Pablo Antonb44b2e02015-02-03 14:13:18 -0300149 enum adv76xx_pad selected_input;
Laurent Pinchart539b33b2014-01-26 18:42:37 -0300150
Hans Verkuil54450f52012-07-18 05:45:16 -0300151 struct v4l2_dv_timings timings;
Pablo Antonb44b2e02015-02-03 14:13:18 -0300152 const struct adv76xx_format_info *format;
Laurent Pinchart539b33b2014-01-26 18:42:37 -0300153
Mats Randgaard4a31a932013-12-10 09:45:00 -0300154 struct {
155 u8 edid[256];
156 u32 present;
157 unsigned blocks;
158 } edid;
Mats Randgaarddd08beb2013-12-10 09:57:09 -0300159 u16 spa_port_a[2];
Hans Verkuil54450f52012-07-18 05:45:16 -0300160 struct v4l2_fract aspect_ratio;
161 u32 rgb_quantization_range;
162 struct workqueue_struct *work_queues;
163 struct delayed_work delayed_work_enable_hotplug;
Hans Verkuilcf9afb12012-10-16 10:12:55 -0300164 bool restart_stdi_once;
Hans Verkuil54450f52012-07-18 05:45:16 -0300165
166 /* i2c clients */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300167 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
Hans Verkuil54450f52012-07-18 05:45:16 -0300168
169 /* controls */
170 struct v4l2_ctrl *detect_tx_5v_ctrl;
171 struct v4l2_ctrl *analog_sampling_phase_ctrl;
172 struct v4l2_ctrl *free_run_color_manual_ctrl;
173 struct v4l2_ctrl *free_run_color_ctrl;
174 struct v4l2_ctrl *rgb_quantization_range_ctrl;
175};
176
Pablo Antonb44b2e02015-02-03 14:13:18 -0300177static bool adv76xx_has_afe(struct adv76xx_state *state)
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300178{
179 return state->info->has_afe;
180}
181
Hans Verkuil54450f52012-07-18 05:45:16 -0300182/* Supported CEA and DMT timings */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300183static const struct v4l2_dv_timings adv76xx_timings[] = {
Hans Verkuil54450f52012-07-18 05:45:16 -0300184 V4L2_DV_BT_CEA_720X480P59_94,
185 V4L2_DV_BT_CEA_720X576P50,
186 V4L2_DV_BT_CEA_1280X720P24,
187 V4L2_DV_BT_CEA_1280X720P25,
Hans Verkuil54450f52012-07-18 05:45:16 -0300188 V4L2_DV_BT_CEA_1280X720P50,
189 V4L2_DV_BT_CEA_1280X720P60,
190 V4L2_DV_BT_CEA_1920X1080P24,
191 V4L2_DV_BT_CEA_1920X1080P25,
192 V4L2_DV_BT_CEA_1920X1080P30,
193 V4L2_DV_BT_CEA_1920X1080P50,
194 V4L2_DV_BT_CEA_1920X1080P60,
195
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300196 /* sorted by DMT ID */
Hans Verkuil54450f52012-07-18 05:45:16 -0300197 V4L2_DV_BT_DMT_640X350P85,
198 V4L2_DV_BT_DMT_640X400P85,
199 V4L2_DV_BT_DMT_720X400P85,
200 V4L2_DV_BT_DMT_640X480P60,
201 V4L2_DV_BT_DMT_640X480P72,
202 V4L2_DV_BT_DMT_640X480P75,
203 V4L2_DV_BT_DMT_640X480P85,
204 V4L2_DV_BT_DMT_800X600P56,
205 V4L2_DV_BT_DMT_800X600P60,
206 V4L2_DV_BT_DMT_800X600P72,
207 V4L2_DV_BT_DMT_800X600P75,
208 V4L2_DV_BT_DMT_800X600P85,
209 V4L2_DV_BT_DMT_848X480P60,
210 V4L2_DV_BT_DMT_1024X768P60,
211 V4L2_DV_BT_DMT_1024X768P70,
212 V4L2_DV_BT_DMT_1024X768P75,
213 V4L2_DV_BT_DMT_1024X768P85,
214 V4L2_DV_BT_DMT_1152X864P75,
215 V4L2_DV_BT_DMT_1280X768P60_RB,
216 V4L2_DV_BT_DMT_1280X768P60,
217 V4L2_DV_BT_DMT_1280X768P75,
218 V4L2_DV_BT_DMT_1280X768P85,
219 V4L2_DV_BT_DMT_1280X800P60_RB,
220 V4L2_DV_BT_DMT_1280X800P60,
221 V4L2_DV_BT_DMT_1280X800P75,
222 V4L2_DV_BT_DMT_1280X800P85,
223 V4L2_DV_BT_DMT_1280X960P60,
224 V4L2_DV_BT_DMT_1280X960P85,
225 V4L2_DV_BT_DMT_1280X1024P60,
226 V4L2_DV_BT_DMT_1280X1024P75,
227 V4L2_DV_BT_DMT_1280X1024P85,
228 V4L2_DV_BT_DMT_1360X768P60,
229 V4L2_DV_BT_DMT_1400X1050P60_RB,
230 V4L2_DV_BT_DMT_1400X1050P60,
231 V4L2_DV_BT_DMT_1400X1050P75,
232 V4L2_DV_BT_DMT_1400X1050P85,
233 V4L2_DV_BT_DMT_1440X900P60_RB,
234 V4L2_DV_BT_DMT_1440X900P60,
235 V4L2_DV_BT_DMT_1600X1200P60,
236 V4L2_DV_BT_DMT_1680X1050P60_RB,
237 V4L2_DV_BT_DMT_1680X1050P60,
238 V4L2_DV_BT_DMT_1792X1344P60,
239 V4L2_DV_BT_DMT_1856X1392P60,
240 V4L2_DV_BT_DMT_1920X1200P60_RB,
Martin Bugge547ed542013-12-05 10:01:17 -0300241 V4L2_DV_BT_DMT_1366X768P60_RB,
Hans Verkuil54450f52012-07-18 05:45:16 -0300242 V4L2_DV_BT_DMT_1366X768P60,
243 V4L2_DV_BT_DMT_1920X1080P60,
244 { },
245};
246
Pablo Antonb44b2e02015-02-03 14:13:18 -0300247struct adv76xx_video_standards {
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300248 struct v4l2_dv_timings timings;
249 u8 vid_std;
250 u8 v_freq;
251};
252
253/* sorted by number of lines */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300254static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300255 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
256 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
257 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
258 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
259 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
260 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
261 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
262 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
263 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
264 /* TODO add 1920x1080P60_RB (CVT timing) */
265 { },
266};
267
268/* sorted by number of lines */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300269static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300270 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
271 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
272 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
273 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
274 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
275 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
276 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
277 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
278 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
279 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
280 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
281 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
282 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
283 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
284 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
285 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
286 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
287 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
288 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
289 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
290 /* TODO add 1600X1200P60_RB (not a DMT timing) */
291 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
292 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
293 { },
294};
295
296/* sorted by number of lines */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300297static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300298 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
299 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
300 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
301 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
302 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
303 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
304 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
305 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
306 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
307 { },
308};
309
310/* sorted by number of lines */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300311static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300312 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
313 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
314 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
315 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
316 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
317 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
318 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
319 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
320 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
321 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
322 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
323 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
324 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
325 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
326 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
327 { },
328};
329
Hans Verkuil54450f52012-07-18 05:45:16 -0300330/* ----------------------------------------------------------------------- */
331
Pablo Antonb44b2e02015-02-03 14:13:18 -0300332static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
Hans Verkuil54450f52012-07-18 05:45:16 -0300333{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300334 return container_of(sd, struct adv76xx_state, sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300335}
336
Hans Verkuil54450f52012-07-18 05:45:16 -0300337static inline unsigned htotal(const struct v4l2_bt_timings *t)
338{
Hans Verkuileacf8f92013-07-29 08:40:59 -0300339 return V4L2_DV_BT_FRAME_WIDTH(t);
Hans Verkuil54450f52012-07-18 05:45:16 -0300340}
341
Hans Verkuil54450f52012-07-18 05:45:16 -0300342static inline unsigned vtotal(const struct v4l2_bt_timings *t)
343{
Hans Verkuileacf8f92013-07-29 08:40:59 -0300344 return V4L2_DV_BT_FRAME_HEIGHT(t);
Hans Verkuil54450f52012-07-18 05:45:16 -0300345}
346
347/* ----------------------------------------------------------------------- */
348
349static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
350 u8 command, bool check)
351{
352 union i2c_smbus_data data;
353
354 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
355 I2C_SMBUS_READ, command,
356 I2C_SMBUS_BYTE_DATA, &data))
357 return data.byte;
358 if (check)
359 v4l_err(client, "error reading %02x, %02x\n",
360 client->addr, command);
361 return -EIO;
362}
363
Pablo Antonb44b2e02015-02-03 14:13:18 -0300364static s32 adv_smbus_read_byte_data(struct adv76xx_state *state,
365 enum adv76xx_page page, u8 command)
Hans Verkuil54450f52012-07-18 05:45:16 -0300366{
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300367 return adv_smbus_read_byte_data_check(state->i2c_clients[page],
368 command, true);
Hans Verkuil54450f52012-07-18 05:45:16 -0300369}
370
Pablo Antonb44b2e02015-02-03 14:13:18 -0300371static s32 adv_smbus_write_byte_data(struct adv76xx_state *state,
372 enum adv76xx_page page, u8 command,
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300373 u8 value)
Hans Verkuil54450f52012-07-18 05:45:16 -0300374{
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300375 struct i2c_client *client = state->i2c_clients[page];
Hans Verkuil54450f52012-07-18 05:45:16 -0300376 union i2c_smbus_data data;
377 int err;
378 int i;
379
380 data.byte = value;
381 for (i = 0; i < 3; i++) {
382 err = i2c_smbus_xfer(client->adapter, client->addr,
383 client->flags,
384 I2C_SMBUS_WRITE, command,
385 I2C_SMBUS_BYTE_DATA, &data);
386 if (!err)
387 break;
388 }
389 if (err < 0)
390 v4l_err(client, "error writing %02x, %02x, %02x\n",
391 client->addr, command, value);
392 return err;
393}
394
Pablo Antonb44b2e02015-02-03 14:13:18 -0300395static s32 adv_smbus_write_i2c_block_data(struct adv76xx_state *state,
396 enum adv76xx_page page, u8 command,
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300397 unsigned length, const u8 *values)
Hans Verkuil54450f52012-07-18 05:45:16 -0300398{
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300399 struct i2c_client *client = state->i2c_clients[page];
Hans Verkuil54450f52012-07-18 05:45:16 -0300400 union i2c_smbus_data data;
401
402 if (length > I2C_SMBUS_BLOCK_MAX)
403 length = I2C_SMBUS_BLOCK_MAX;
404 data.block[0] = length;
405 memcpy(data.block + 1, values, length);
406 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
407 I2C_SMBUS_WRITE, command,
408 I2C_SMBUS_I2C_BLOCK_DATA, &data);
409}
410
411/* ----------------------------------------------------------------------- */
412
413static inline int io_read(struct v4l2_subdev *sd, u8 reg)
414{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300415 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300416
Pablo Antonb44b2e02015-02-03 14:13:18 -0300417 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_IO, reg);
Hans Verkuil54450f52012-07-18 05:45:16 -0300418}
419
420static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
421{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300422 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300423
Pablo Antonb44b2e02015-02-03 14:13:18 -0300424 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_IO, reg, val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300425}
426
Laurent Pinchart22d97e52014-01-30 17:17:42 -0300427static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
Hans Verkuil54450f52012-07-18 05:45:16 -0300428{
Laurent Pinchart22d97e52014-01-30 17:17:42 -0300429 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300430}
431
432static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
433{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300434 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300435
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300436 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
Hans Verkuil54450f52012-07-18 05:45:16 -0300437}
438
439static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
440{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300441 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300442
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300443 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300444}
445
446static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
447{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300448 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300449
Pablo Antonb44b2e02015-02-03 14:13:18 -0300450 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CEC, reg);
Hans Verkuil54450f52012-07-18 05:45:16 -0300451}
452
453static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
454{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300455 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300456
Pablo Antonb44b2e02015-02-03 14:13:18 -0300457 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CEC, reg, val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300458}
459
Hans Verkuil54450f52012-07-18 05:45:16 -0300460static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
461{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300462 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300463
Pablo Antonb44b2e02015-02-03 14:13:18 -0300464 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_INFOFRAME, reg);
Hans Verkuil54450f52012-07-18 05:45:16 -0300465}
466
467static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
468{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300469 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300470
Pablo Antonb44b2e02015-02-03 14:13:18 -0300471 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_INFOFRAME,
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300472 reg, val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300473}
474
Hans Verkuil54450f52012-07-18 05:45:16 -0300475static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
476{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300477 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300478
Pablo Antonb44b2e02015-02-03 14:13:18 -0300479 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_AFE, reg);
Hans Verkuil54450f52012-07-18 05:45:16 -0300480}
481
482static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
483{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300484 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300485
Pablo Antonb44b2e02015-02-03 14:13:18 -0300486 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_AFE, reg, val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300487}
488
489static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
490{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300491 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300492
Pablo Antonb44b2e02015-02-03 14:13:18 -0300493 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_REP, reg);
Hans Verkuil54450f52012-07-18 05:45:16 -0300494}
495
496static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
497{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300498 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300499
Pablo Antonb44b2e02015-02-03 14:13:18 -0300500 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_REP, reg, val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300501}
502
Laurent Pinchart22d97e52014-01-30 17:17:42 -0300503static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
Hans Verkuil54450f52012-07-18 05:45:16 -0300504{
Laurent Pinchart22d97e52014-01-30 17:17:42 -0300505 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300506}
507
508static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
509{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300510 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300511
Pablo Antonb44b2e02015-02-03 14:13:18 -0300512 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_EDID, reg);
Hans Verkuil54450f52012-07-18 05:45:16 -0300513}
514
515static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
516{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300517 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300518
Pablo Antonb44b2e02015-02-03 14:13:18 -0300519 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_EDID, reg, val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300520}
521
Mats Randgaarddd08beb2013-12-10 09:57:09 -0300522static inline int edid_write_block(struct v4l2_subdev *sd,
523 unsigned len, const u8 *val)
524{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300525 struct adv76xx_state *state = to_state(sd);
Mats Randgaarddd08beb2013-12-10 09:57:09 -0300526 int err = 0;
527 int i;
528
529 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
530
531 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
Pablo Antonb44b2e02015-02-03 14:13:18 -0300532 err = adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_EDID,
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300533 i, I2C_SMBUS_BLOCK_MAX, val + i);
Mats Randgaarddd08beb2013-12-10 09:57:09 -0300534 return err;
535}
536
Pablo Antonb44b2e02015-02-03 14:13:18 -0300537static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
Laurent Pincharte9d50e92014-01-30 18:37:08 -0300538{
539 unsigned int i;
540
Uwe Kleine-König269bd132015-03-02 04:00:44 -0300541 for (i = 0; i < state->info->num_dv_ports; ++i)
Laurent Pincharte9d50e92014-01-30 18:37:08 -0300542 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
Laurent Pincharte9d50e92014-01-30 18:37:08 -0300543
Pablo Antonb44b2e02015-02-03 14:13:18 -0300544 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
Laurent Pincharte9d50e92014-01-30 18:37:08 -0300545}
546
Pablo Antonb44b2e02015-02-03 14:13:18 -0300547static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
Hans Verkuil54450f52012-07-18 05:45:16 -0300548{
549 struct delayed_work *dwork = to_delayed_work(work);
Pablo Antonb44b2e02015-02-03 14:13:18 -0300550 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
Hans Verkuil54450f52012-07-18 05:45:16 -0300551 delayed_work_enable_hotplug);
552 struct v4l2_subdev *sd = &state->sd;
553
554 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
555
Pablo Antonb44b2e02015-02-03 14:13:18 -0300556 adv76xx_set_hpd(state, state->edid.present);
Hans Verkuil54450f52012-07-18 05:45:16 -0300557}
558
Hans Verkuil54450f52012-07-18 05:45:16 -0300559static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
560{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300561 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300562
Pablo Antonb44b2e02015-02-03 14:13:18 -0300563 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_HDMI, reg);
Hans Verkuil54450f52012-07-18 05:45:16 -0300564}
565
Laurent Pinchart51182a92014-01-08 19:30:37 -0300566static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
567{
568 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
569}
570
Hans Verkuil54450f52012-07-18 05:45:16 -0300571static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
572{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300573 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300574
Pablo Antonb44b2e02015-02-03 14:13:18 -0300575 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_HDMI, reg, val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300576}
577
Laurent Pinchart22d97e52014-01-30 17:17:42 -0300578static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
Mats Randgaard4a31a932013-12-10 09:45:00 -0300579{
Laurent Pinchart22d97e52014-01-30 17:17:42 -0300580 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
Mats Randgaard4a31a932013-12-10 09:45:00 -0300581}
582
Hans Verkuil54450f52012-07-18 05:45:16 -0300583static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
584{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300585 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300586
Pablo Antonb44b2e02015-02-03 14:13:18 -0300587 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_TEST, reg, val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300588}
589
590static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
591{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300592 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300593
Pablo Antonb44b2e02015-02-03 14:13:18 -0300594 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CP, reg);
Hans Verkuil54450f52012-07-18 05:45:16 -0300595}
596
Laurent Pinchart51182a92014-01-08 19:30:37 -0300597static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
598{
599 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
600}
601
Hans Verkuil54450f52012-07-18 05:45:16 -0300602static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
603{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300604 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300605
Pablo Antonb44b2e02015-02-03 14:13:18 -0300606 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CP, reg, val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300607}
608
Laurent Pinchart22d97e52014-01-30 17:17:42 -0300609static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
Hans Verkuil54450f52012-07-18 05:45:16 -0300610{
Laurent Pinchart22d97e52014-01-30 17:17:42 -0300611 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300612}
613
614static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
615{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300616 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300617
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300618 return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
Hans Verkuil54450f52012-07-18 05:45:16 -0300619}
620
621static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
622{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300623 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -0300624
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300625 return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
Hans Verkuil54450f52012-07-18 05:45:16 -0300626}
627
Pablo Antonb44b2e02015-02-03 14:13:18 -0300628#define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
629#define ADV76XX_REG_SEQ_TERM 0xffff
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300630
631#ifdef CONFIG_VIDEO_ADV_DEBUG
Pablo Antonb44b2e02015-02-03 14:13:18 -0300632static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300633{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300634 struct adv76xx_state *state = to_state(sd);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300635 unsigned int page = reg >> 8;
636
637 if (!(BIT(page) & state->info->page_mask))
638 return -EINVAL;
639
640 reg &= 0xff;
641
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300642 return adv_smbus_read_byte_data(state, page, reg);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300643}
644#endif
645
Pablo Antonb44b2e02015-02-03 14:13:18 -0300646static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300647{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300648 struct adv76xx_state *state = to_state(sd);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300649 unsigned int page = reg >> 8;
650
651 if (!(BIT(page) & state->info->page_mask))
652 return -EINVAL;
653
654 reg &= 0xff;
655
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300656 return adv_smbus_write_byte_data(state, page, reg, val);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300657}
658
Pablo Antonb44b2e02015-02-03 14:13:18 -0300659static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
660 const struct adv76xx_reg_seq *reg_seq)
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300661{
662 unsigned int i;
663
Pablo Antonb44b2e02015-02-03 14:13:18 -0300664 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
665 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300666}
667
Laurent Pinchart539b33b2014-01-26 18:42:37 -0300668/* -----------------------------------------------------------------------------
669 * Format helpers
670 */
671
Pablo Antonb44b2e02015-02-03 14:13:18 -0300672static const struct adv76xx_format_info adv7604_formats[] = {
673 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
674 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
675 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
676 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
677 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
678 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
679 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
680 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
681 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
682 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
683 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
684 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
685 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
686 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
687 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
688 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
689 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
690 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
691 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
692 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
693 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
694 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
695 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
696 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
697 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
698 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
699 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
700 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
701 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
702 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
703 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
704 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
705 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
706 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
707 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
708 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
709 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
710 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
Laurent Pinchart539b33b2014-01-26 18:42:37 -0300711};
712
Pablo Antonb44b2e02015-02-03 14:13:18 -0300713static const struct adv76xx_format_info adv7611_formats[] = {
714 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
715 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
716 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
717 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
718 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
719 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
720 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
721 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
722 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
723 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
724 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
725 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
726 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
727 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
728 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
729 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
730 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
731 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
732 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
733 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
734 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
735 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
736 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
737 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
738 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
739 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
Laurent Pinchart539b33b2014-01-26 18:42:37 -0300740};
741
Pablo Antonb44b2e02015-02-03 14:13:18 -0300742static const struct adv76xx_format_info *
743adv76xx_format_info(struct adv76xx_state *state, u32 code)
Laurent Pinchart539b33b2014-01-26 18:42:37 -0300744{
745 unsigned int i;
746
747 for (i = 0; i < state->info->nformats; ++i) {
748 if (state->info->formats[i].code == code)
749 return &state->info->formats[i];
750 }
751
752 return NULL;
753}
754
Hans Verkuil54450f52012-07-18 05:45:16 -0300755/* ----------------------------------------------------------------------- */
756
Mats Randgaard4a31a932013-12-10 09:45:00 -0300757static inline bool is_analog_input(struct v4l2_subdev *sd)
758{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300759 struct adv76xx_state *state = to_state(sd);
Mats Randgaard4a31a932013-12-10 09:45:00 -0300760
Laurent Pinchartc784b1e2014-01-29 10:08:58 -0300761 return state->selected_input == ADV7604_PAD_VGA_RGB ||
762 state->selected_input == ADV7604_PAD_VGA_COMP;
Mats Randgaard4a31a932013-12-10 09:45:00 -0300763}
764
765static inline bool is_digital_input(struct v4l2_subdev *sd)
766{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300767 struct adv76xx_state *state = to_state(sd);
Mats Randgaard4a31a932013-12-10 09:45:00 -0300768
Pablo Antonb44b2e02015-02-03 14:13:18 -0300769 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
Laurent Pinchartc784b1e2014-01-29 10:08:58 -0300770 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
771 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
772 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
Mats Randgaard4a31a932013-12-10 09:45:00 -0300773}
774
775/* ----------------------------------------------------------------------- */
776
Hans Verkuil54450f52012-07-18 05:45:16 -0300777#ifdef CONFIG_VIDEO_ADV_DEBUG
Pablo Antonb44b2e02015-02-03 14:13:18 -0300778static void adv76xx_inv_register(struct v4l2_subdev *sd)
Hans Verkuil54450f52012-07-18 05:45:16 -0300779{
780 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
781 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
782 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
783 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
784 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
785 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
786 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
787 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
788 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
789 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
790 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
791 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
792 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
793}
794
Pablo Antonb44b2e02015-02-03 14:13:18 -0300795static int adv76xx_g_register(struct v4l2_subdev *sd,
Hans Verkuil54450f52012-07-18 05:45:16 -0300796 struct v4l2_dbg_register *reg)
797{
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300798 int ret;
799
Pablo Antonb44b2e02015-02-03 14:13:18 -0300800 ret = adv76xx_read_reg(sd, reg->reg);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300801 if (ret < 0) {
Hans Verkuil54450f52012-07-18 05:45:16 -0300802 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
Pablo Antonb44b2e02015-02-03 14:13:18 -0300803 adv76xx_inv_register(sd);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300804 return ret;
Hans Verkuil54450f52012-07-18 05:45:16 -0300805 }
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300806
807 reg->size = 1;
808 reg->val = ret;
809
Hans Verkuil54450f52012-07-18 05:45:16 -0300810 return 0;
811}
812
Pablo Antonb44b2e02015-02-03 14:13:18 -0300813static int adv76xx_s_register(struct v4l2_subdev *sd,
Hans Verkuil977ba3b2013-03-24 08:28:46 -0300814 const struct v4l2_dbg_register *reg)
Hans Verkuil54450f52012-07-18 05:45:16 -0300815{
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300816 int ret;
Hans Verkuil15774612013-12-10 10:02:43 -0300817
Pablo Antonb44b2e02015-02-03 14:13:18 -0300818 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300819 if (ret < 0) {
Hans Verkuil54450f52012-07-18 05:45:16 -0300820 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
Pablo Antonb44b2e02015-02-03 14:13:18 -0300821 adv76xx_inv_register(sd);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300822 return ret;
Hans Verkuil54450f52012-07-18 05:45:16 -0300823 }
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300824
Hans Verkuil54450f52012-07-18 05:45:16 -0300825 return 0;
826}
827#endif
828
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300829static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
830{
831 u8 value = io_read(sd, 0x6f);
832
833 return ((value & 0x10) >> 4)
834 | ((value & 0x08) >> 2)
835 | ((value & 0x04) << 0)
836 | ((value & 0x02) << 2);
837}
838
839static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
840{
841 u8 value = io_read(sd, 0x6f);
842
843 return value & 1;
844}
845
Pablo Antonb44b2e02015-02-03 14:13:18 -0300846static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
Hans Verkuil54450f52012-07-18 05:45:16 -0300847{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300848 struct adv76xx_state *state = to_state(sd);
849 const struct adv76xx_chip_info *info = state->info;
Hans Verkuil54450f52012-07-18 05:45:16 -0300850
Hans Verkuil54450f52012-07-18 05:45:16 -0300851 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300852 info->read_cable_det(sd));
Hans Verkuil54450f52012-07-18 05:45:16 -0300853}
854
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300855static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
856 u8 prim_mode,
Pablo Antonb44b2e02015-02-03 14:13:18 -0300857 const struct adv76xx_video_standards *predef_vid_timings,
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300858 const struct v4l2_dv_timings *timings)
Hans Verkuil54450f52012-07-18 05:45:16 -0300859{
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300860 int i;
861
862 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
Hans Verkuilef1ed8f2013-08-15 08:28:47 -0300863 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
Mats Randgaard4a31a932013-12-10 09:45:00 -0300864 is_digital_input(sd) ? 250000 : 1000000))
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300865 continue;
866 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
867 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
868 prim_mode); /* v_freq and prim mode */
869 return 0;
870 }
871
872 return -1;
873}
874
875static int configure_predefined_video_timings(struct v4l2_subdev *sd,
876 struct v4l2_dv_timings *timings)
877{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300878 struct adv76xx_state *state = to_state(sd);
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300879 int err;
880
881 v4l2_dbg(1, debug, sd, "%s", __func__);
882
Pablo Antonb44b2e02015-02-03 14:13:18 -0300883 if (adv76xx_has_afe(state)) {
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300884 /* reset to default values */
885 io_write(sd, 0x16, 0x43);
886 io_write(sd, 0x17, 0x5a);
887 }
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300888 /* disable embedded syncs for auto graphics mode */
Laurent Pinchart22d97e52014-01-30 17:17:42 -0300889 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300890 cp_write(sd, 0x8f, 0x00);
891 cp_write(sd, 0x90, 0x00);
892 cp_write(sd, 0xa2, 0x00);
893 cp_write(sd, 0xa3, 0x00);
894 cp_write(sd, 0xa4, 0x00);
895 cp_write(sd, 0xa5, 0x00);
896 cp_write(sd, 0xa6, 0x00);
897 cp_write(sd, 0xa7, 0x00);
898 cp_write(sd, 0xab, 0x00);
899 cp_write(sd, 0xac, 0x00);
900
Mats Randgaard4a31a932013-12-10 09:45:00 -0300901 if (is_analog_input(sd)) {
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300902 err = find_and_set_predefined_video_timings(sd,
903 0x01, adv7604_prim_mode_comp, timings);
904 if (err)
905 err = find_and_set_predefined_video_timings(sd,
906 0x02, adv7604_prim_mode_gr, timings);
Mats Randgaard4a31a932013-12-10 09:45:00 -0300907 } else if (is_digital_input(sd)) {
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300908 err = find_and_set_predefined_video_timings(sd,
Pablo Antonb44b2e02015-02-03 14:13:18 -0300909 0x05, adv76xx_prim_mode_hdmi_comp, timings);
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300910 if (err)
911 err = find_and_set_predefined_video_timings(sd,
Pablo Antonb44b2e02015-02-03 14:13:18 -0300912 0x06, adv76xx_prim_mode_hdmi_gr, timings);
Mats Randgaard4a31a932013-12-10 09:45:00 -0300913 } else {
914 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
915 __func__, state->selected_input);
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300916 err = -1;
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300917 }
918
919
920 return err;
921}
922
923static void configure_custom_video_timings(struct v4l2_subdev *sd,
924 const struct v4l2_bt_timings *bt)
925{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300926 struct adv76xx_state *state = to_state(sd);
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300927 u32 width = htotal(bt);
928 u32 height = vtotal(bt);
929 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
930 u16 cp_start_eav = width - bt->hfrontporch;
931 u16 cp_start_vbi = height - bt->vfrontporch;
932 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
933 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
Pablo Antonb44b2e02015-02-03 14:13:18 -0300934 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300935 const u8 pll[2] = {
936 0xc0 | ((width >> 8) & 0x1f),
937 width & 0xff
938 };
Hans Verkuil54450f52012-07-18 05:45:16 -0300939
940 v4l2_dbg(2, debug, sd, "%s\n", __func__);
941
Mats Randgaard4a31a932013-12-10 09:45:00 -0300942 if (is_analog_input(sd)) {
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300943 /* auto graphics */
944 io_write(sd, 0x00, 0x07); /* video std */
945 io_write(sd, 0x01, 0x02); /* prim mode */
946 /* enable embedded syncs for auto graphics mode */
Laurent Pinchart22d97e52014-01-30 17:17:42 -0300947 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
Hans Verkuil54450f52012-07-18 05:45:16 -0300948
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300949 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
Hans Verkuil54450f52012-07-18 05:45:16 -0300950 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
951 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300952 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_IO,
Laurent Pinchart05cacb12014-01-30 16:32:21 -0300953 0x16, 2, pll))
Hans Verkuil54450f52012-07-18 05:45:16 -0300954 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
Hans Verkuil54450f52012-07-18 05:45:16 -0300955
956 /* active video - horizontal timing */
Hans Verkuil54450f52012-07-18 05:45:16 -0300957 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300958 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
Mats Randgaard4a31a932013-12-10 09:45:00 -0300959 ((cp_start_eav >> 8) & 0x0f));
Hans Verkuil54450f52012-07-18 05:45:16 -0300960 cp_write(sd, 0xa4, cp_start_eav & 0xff);
961
962 /* active video - vertical timing */
Hans Verkuil54450f52012-07-18 05:45:16 -0300963 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300964 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
Mats Randgaard4a31a932013-12-10 09:45:00 -0300965 ((cp_end_vbi >> 8) & 0xf));
Hans Verkuil54450f52012-07-18 05:45:16 -0300966 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
Mats Randgaard4a31a932013-12-10 09:45:00 -0300967 } else if (is_digital_input(sd)) {
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300968 /* set default prim_mode/vid_std for HDMI
Jonathan McCrohan39c1cb22013-10-20 21:34:01 -0300969 according to [REF_03, c. 4.2] */
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300970 io_write(sd, 0x00, 0x02); /* video std */
971 io_write(sd, 0x01, 0x06); /* prim mode */
Mats Randgaard4a31a932013-12-10 09:45:00 -0300972 } else {
973 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
974 __func__, state->selected_input);
Hans Verkuil54450f52012-07-18 05:45:16 -0300975 }
Hans Verkuil54450f52012-07-18 05:45:16 -0300976
Hans Verkuilccbd5bc2012-10-16 10:02:05 -0300977 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
978 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
979 cp_write(sd, 0xab, (height >> 4) & 0xff);
980 cp_write(sd, 0xac, (height & 0x0f) << 4);
981}
Hans Verkuil54450f52012-07-18 05:45:16 -0300982
Pablo Antonb44b2e02015-02-03 14:13:18 -0300983static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
Mats Randgaard5c6c6342013-12-05 10:39:04 -0300984{
Pablo Antonb44b2e02015-02-03 14:13:18 -0300985 struct adv76xx_state *state = to_state(sd);
Mats Randgaard5c6c6342013-12-05 10:39:04 -0300986 u8 offset_buf[4];
987
988 if (auto_offset) {
989 offset_a = 0x3ff;
990 offset_b = 0x3ff;
991 offset_c = 0x3ff;
992 }
993
994 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
995 __func__, auto_offset ? "Auto" : "Manual",
996 offset_a, offset_b, offset_c);
997
998 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
999 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1000 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1001 offset_buf[3] = offset_c & 0x0ff;
1002
1003 /* Registers must be written in this order with no i2c access in between */
Pablo Antonb44b2e02015-02-03 14:13:18 -03001004 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
Laurent Pinchart05cacb12014-01-30 16:32:21 -03001005 0x77, 4, offset_buf))
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001006 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1007}
1008
Pablo Antonb44b2e02015-02-03 14:13:18 -03001009static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001010{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001011 struct adv76xx_state *state = to_state(sd);
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001012 u8 gain_buf[4];
1013 u8 gain_man = 1;
1014 u8 agc_mode_man = 1;
1015
1016 if (auto_gain) {
1017 gain_man = 0;
1018 agc_mode_man = 0;
1019 gain_a = 0x100;
1020 gain_b = 0x100;
1021 gain_c = 0x100;
1022 }
1023
1024 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1025 __func__, auto_gain ? "Auto" : "Manual",
1026 gain_a, gain_b, gain_c);
1027
1028 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1029 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1030 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1031 gain_buf[3] = ((gain_c & 0x0ff));
1032
1033 /* Registers must be written in this order with no i2c access in between */
Pablo Antonb44b2e02015-02-03 14:13:18 -03001034 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
Laurent Pinchart05cacb12014-01-30 16:32:21 -03001035 0x73, 4, gain_buf))
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001036 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1037}
1038
Hans Verkuil54450f52012-07-18 05:45:16 -03001039static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1040{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001041 struct adv76xx_state *state = to_state(sd);
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001042 bool rgb_output = io_read(sd, 0x02) & 0x02;
1043 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
Hans Verkuil54450f52012-07-18 05:45:16 -03001044
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001045 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1046 __func__, state->rgb_quantization_range,
1047 rgb_output, hdmi_signal);
1048
Pablo Antonb44b2e02015-02-03 14:13:18 -03001049 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1050 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
Mats Randgaard98332392013-12-05 10:05:58 -03001051
Hans Verkuil54450f52012-07-18 05:45:16 -03001052 switch (state->rgb_quantization_range) {
1053 case V4L2_DV_RGB_RANGE_AUTO:
Laurent Pinchartc784b1e2014-01-29 10:08:58 -03001054 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
Mats Randgaard98332392013-12-05 10:05:58 -03001055 /* Receiving analog RGB signal
1056 * Set RGB full range (0-255) */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001057 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
Mats Randgaard98332392013-12-05 10:05:58 -03001058 break;
1059 }
Hans Verkuil54450f52012-07-18 05:45:16 -03001060
Laurent Pinchartc784b1e2014-01-29 10:08:58 -03001061 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
Mats Randgaard98332392013-12-05 10:05:58 -03001062 /* Receiving analog YPbPr signal
1063 * Set automode */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001064 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
Mats Randgaard98332392013-12-05 10:05:58 -03001065 break;
1066 }
1067
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001068 if (hdmi_signal) {
Mats Randgaard98332392013-12-05 10:05:58 -03001069 /* Receiving HDMI signal
1070 * Set automode */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001071 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
Mats Randgaard98332392013-12-05 10:05:58 -03001072 break;
1073 }
1074
1075 /* Receiving DVI-D signal
1076 * ADV7604 selects RGB limited range regardless of
1077 * input format (CE/IT) in automatic mode */
1078 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1079 /* RGB limited range (16-235) */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001080 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
Mats Randgaard98332392013-12-05 10:05:58 -03001081 } else {
1082 /* RGB full range (0-255) */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001083 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001084
1085 if (is_digital_input(sd) && rgb_output) {
Pablo Antonb44b2e02015-02-03 14:13:18 -03001086 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001087 } else {
Pablo Antonb44b2e02015-02-03 14:13:18 -03001088 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1089 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001090 }
Hans Verkuil54450f52012-07-18 05:45:16 -03001091 }
1092 break;
1093 case V4L2_DV_RGB_RANGE_LIMITED:
Laurent Pinchartc784b1e2014-01-29 10:08:58 -03001094 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
Mats Randgaardd261e842013-12-05 10:17:15 -03001095 /* YCrCb limited range (16-235) */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001096 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001097 break;
Mats Randgaardd261e842013-12-05 10:17:15 -03001098 }
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001099
1100 /* RGB limited range (16-235) */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001101 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001102
Hans Verkuil54450f52012-07-18 05:45:16 -03001103 break;
1104 case V4L2_DV_RGB_RANGE_FULL:
Laurent Pinchartc784b1e2014-01-29 10:08:58 -03001105 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
Mats Randgaardd261e842013-12-05 10:17:15 -03001106 /* YCrCb full range (0-255) */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001107 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001108 break;
1109 }
1110
1111 /* RGB full range (0-255) */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001112 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
Mats Randgaard5c6c6342013-12-05 10:39:04 -03001113
1114 if (is_analog_input(sd) || hdmi_signal)
1115 break;
1116
1117 /* Adjust gain/offset for DVI-D signals only */
1118 if (rgb_output) {
Pablo Antonb44b2e02015-02-03 14:13:18 -03001119 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
Mats Randgaardd261e842013-12-05 10:17:15 -03001120 } else {
Pablo Antonb44b2e02015-02-03 14:13:18 -03001121 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1122 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
Mats Randgaardd261e842013-12-05 10:17:15 -03001123 }
Hans Verkuil54450f52012-07-18 05:45:16 -03001124 break;
1125 }
1126}
1127
Pablo Antonb44b2e02015-02-03 14:13:18 -03001128static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
Hans Verkuil54450f52012-07-18 05:45:16 -03001129{
Laurent Pinchartc2698872014-01-30 15:16:03 -03001130 struct v4l2_subdev *sd =
Pablo Antonb44b2e02015-02-03 14:13:18 -03001131 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
Laurent Pinchartc2698872014-01-30 15:16:03 -03001132
Pablo Antonb44b2e02015-02-03 14:13:18 -03001133 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -03001134
1135 switch (ctrl->id) {
1136 case V4L2_CID_BRIGHTNESS:
1137 cp_write(sd, 0x3c, ctrl->val);
1138 return 0;
1139 case V4L2_CID_CONTRAST:
1140 cp_write(sd, 0x3a, ctrl->val);
1141 return 0;
1142 case V4L2_CID_SATURATION:
1143 cp_write(sd, 0x3b, ctrl->val);
1144 return 0;
1145 case V4L2_CID_HUE:
1146 cp_write(sd, 0x3d, ctrl->val);
1147 return 0;
1148 case V4L2_CID_DV_RX_RGB_RANGE:
1149 state->rgb_quantization_range = ctrl->val;
1150 set_rgb_quantization_range(sd);
1151 return 0;
1152 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
Pablo Antonb44b2e02015-02-03 14:13:18 -03001153 if (!adv76xx_has_afe(state))
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001154 return -EINVAL;
Hans Verkuil54450f52012-07-18 05:45:16 -03001155 /* Set the analog sampling phase. This is needed to find the
1156 best sampling phase for analog video: an application or
1157 driver has to try a number of phases and analyze the picture
1158 quality before settling on the best performing phase. */
1159 afe_write(sd, 0xc8, ctrl->val);
1160 return 0;
1161 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1162 /* Use the default blue color for free running mode,
1163 or supply your own. */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001164 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
Hans Verkuil54450f52012-07-18 05:45:16 -03001165 return 0;
1166 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1167 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1168 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1169 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1170 return 0;
1171 }
1172 return -EINVAL;
1173}
1174
Hans Verkuil54450f52012-07-18 05:45:16 -03001175/* ----------------------------------------------------------------------- */
1176
1177static inline bool no_power(struct v4l2_subdev *sd)
1178{
1179 /* Entire chip or CP powered off */
1180 return io_read(sd, 0x0c) & 0x24;
1181}
1182
1183static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1184{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001185 struct adv76xx_state *state = to_state(sd);
Mats Randgaard4a31a932013-12-10 09:45:00 -03001186
1187 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
Hans Verkuil54450f52012-07-18 05:45:16 -03001188}
1189
1190static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1191{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001192 struct adv76xx_state *state = to_state(sd);
1193 const struct adv76xx_chip_info *info = state->info;
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001194
1195 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
Hans Verkuil54450f52012-07-18 05:45:16 -03001196}
1197
Martin Buggebb88f322013-08-14 08:52:46 -03001198static inline bool is_hdmi(struct v4l2_subdev *sd)
1199{
1200 return hdmi_read(sd, 0x05) & 0x80;
1201}
1202
Hans Verkuil54450f52012-07-18 05:45:16 -03001203static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1204{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001205 struct adv76xx_state *state = to_state(sd);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001206
1207 /*
1208 * Chips without a AFE don't expose registers for the SSPD, so just assume
1209 * that we have a lock.
1210 */
Pablo Antonb44b2e02015-02-03 14:13:18 -03001211 if (adv76xx_has_afe(state))
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001212 return false;
1213
Hans Verkuil54450f52012-07-18 05:45:16 -03001214 /* TODO channel 2 */
1215 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1216}
1217
1218static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1219{
1220 /* TODO channel 2 */
1221 return !(cp_read(sd, 0xb1) & 0x80);
1222}
1223
1224static inline bool no_signal(struct v4l2_subdev *sd)
1225{
Hans Verkuil54450f52012-07-18 05:45:16 -03001226 bool ret;
1227
1228 ret = no_power(sd);
1229
1230 ret |= no_lock_stdi(sd);
1231 ret |= no_lock_sspd(sd);
1232
Mats Randgaard4a31a932013-12-10 09:45:00 -03001233 if (is_digital_input(sd)) {
Hans Verkuil54450f52012-07-18 05:45:16 -03001234 ret |= no_lock_tmds(sd);
1235 ret |= no_signal_tmds(sd);
1236 }
1237
1238 return ret;
1239}
1240
1241static inline bool no_lock_cp(struct v4l2_subdev *sd)
1242{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001243 struct adv76xx_state *state = to_state(sd);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001244
Pablo Antonb44b2e02015-02-03 14:13:18 -03001245 if (!adv76xx_has_afe(state))
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001246 return false;
1247
Hans Verkuil54450f52012-07-18 05:45:16 -03001248 /* CP has detected a non standard number of lines on the incoming
1249 video compared to what it is configured to receive by s_dv_timings */
1250 return io_read(sd, 0x12) & 0x01;
1251}
1252
jean-michel.hautbois@vodalys.com58514622015-02-06 11:37:58 -03001253static inline bool in_free_run(struct v4l2_subdev *sd)
1254{
1255 return cp_read(sd, 0xff) & 0x10;
1256}
1257
Pablo Antonb44b2e02015-02-03 14:13:18 -03001258static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
Hans Verkuil54450f52012-07-18 05:45:16 -03001259{
Hans Verkuil54450f52012-07-18 05:45:16 -03001260 *status = 0;
1261 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1262 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
jean-michel.hautbois@vodalys.com58514622015-02-06 11:37:58 -03001263 if (!in_free_run(sd) && no_lock_cp(sd))
1264 *status |= is_digital_input(sd) ?
1265 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
Hans Verkuil54450f52012-07-18 05:45:16 -03001266
1267 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1268
1269 return 0;
1270}
1271
1272/* ----------------------------------------------------------------------- */
1273
Hans Verkuil54450f52012-07-18 05:45:16 -03001274struct stdi_readback {
1275 u16 bl, lcf, lcvs;
1276 u8 hs_pol, vs_pol;
1277 bool interlaced;
1278};
1279
1280static int stdi2dv_timings(struct v4l2_subdev *sd,
1281 struct stdi_readback *stdi,
1282 struct v4l2_dv_timings *timings)
1283{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001284 struct adv76xx_state *state = to_state(sd);
1285 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
Hans Verkuil54450f52012-07-18 05:45:16 -03001286 u32 pix_clk;
1287 int i;
1288
Pablo Antonb44b2e02015-02-03 14:13:18 -03001289 for (i = 0; adv76xx_timings[i].bt.height; i++) {
1290 if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1)
Hans Verkuil54450f52012-07-18 05:45:16 -03001291 continue;
Pablo Antonb44b2e02015-02-03 14:13:18 -03001292 if (adv76xx_timings[i].bt.vsync != stdi->lcvs)
Hans Verkuil54450f52012-07-18 05:45:16 -03001293 continue;
1294
Pablo Antonb44b2e02015-02-03 14:13:18 -03001295 pix_clk = hfreq * htotal(&adv76xx_timings[i].bt);
Hans Verkuil54450f52012-07-18 05:45:16 -03001296
Pablo Antonb44b2e02015-02-03 14:13:18 -03001297 if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) &&
1298 (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) {
1299 *timings = adv76xx_timings[i];
Hans Verkuil54450f52012-07-18 05:45:16 -03001300 return 0;
1301 }
1302 }
1303
1304 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1305 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1306 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1307 timings))
1308 return 0;
1309 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1310 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1311 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1312 state->aspect_ratio, timings))
1313 return 0;
1314
Hans Verkuilccbd5bc2012-10-16 10:02:05 -03001315 v4l2_dbg(2, debug, sd,
1316 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1317 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1318 stdi->hs_pol, stdi->vs_pol);
Hans Verkuil54450f52012-07-18 05:45:16 -03001319 return -1;
1320}
1321
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001322
Hans Verkuil54450f52012-07-18 05:45:16 -03001323static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1324{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001325 struct adv76xx_state *state = to_state(sd);
1326 const struct adv76xx_chip_info *info = state->info;
Laurent Pinchart4a2ccdd2014-01-08 20:26:55 -03001327 u8 polarity;
1328
Hans Verkuil54450f52012-07-18 05:45:16 -03001329 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1330 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1331 return -1;
1332 }
1333
1334 /* read STDI */
Laurent Pinchart51182a92014-01-08 19:30:37 -03001335 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001336 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
Hans Verkuil54450f52012-07-18 05:45:16 -03001337 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1338 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1339
Pablo Antonb44b2e02015-02-03 14:13:18 -03001340 if (adv76xx_has_afe(state)) {
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001341 /* read SSPD */
1342 polarity = cp_read(sd, 0xb5);
1343 if ((polarity & 0x03) == 0x01) {
1344 stdi->hs_pol = polarity & 0x10
1345 ? (polarity & 0x08 ? '+' : '-') : 'x';
1346 stdi->vs_pol = polarity & 0x40
1347 ? (polarity & 0x20 ? '+' : '-') : 'x';
1348 } else {
1349 stdi->hs_pol = 'x';
1350 stdi->vs_pol = 'x';
1351 }
Hans Verkuil54450f52012-07-18 05:45:16 -03001352 } else {
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001353 polarity = hdmi_read(sd, 0x05);
1354 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1355 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
Hans Verkuil54450f52012-07-18 05:45:16 -03001356 }
1357
1358 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1359 v4l2_dbg(2, debug, sd,
1360 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1361 return -1;
1362 }
1363
1364 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1365 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1366 memset(stdi, 0, sizeof(struct stdi_readback));
1367 return -1;
1368 }
1369
1370 v4l2_dbg(2, debug, sd,
1371 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1372 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1373 stdi->hs_pol, stdi->vs_pol,
1374 stdi->interlaced ? "interlaced" : "progressive");
1375
1376 return 0;
1377}
1378
Pablo Antonb44b2e02015-02-03 14:13:18 -03001379static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
Hans Verkuil54450f52012-07-18 05:45:16 -03001380 struct v4l2_enum_dv_timings *timings)
1381{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001382 struct adv76xx_state *state = to_state(sd);
Laurent Pinchartafec5592014-01-29 10:09:41 -03001383
Pablo Antonb44b2e02015-02-03 14:13:18 -03001384 if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1)
Hans Verkuil54450f52012-07-18 05:45:16 -03001385 return -EINVAL;
Laurent Pinchartafec5592014-01-29 10:09:41 -03001386
1387 if (timings->pad >= state->source_pad)
1388 return -EINVAL;
1389
Hans Verkuil54450f52012-07-18 05:45:16 -03001390 memset(timings->reserved, 0, sizeof(timings->reserved));
Pablo Antonb44b2e02015-02-03 14:13:18 -03001391 timings->timings = adv76xx_timings[timings->index];
Hans Verkuil54450f52012-07-18 05:45:16 -03001392 return 0;
1393}
1394
Pablo Antonb44b2e02015-02-03 14:13:18 -03001395static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
Laurent Pinchart7515e092014-01-31 08:51:18 -03001396 struct v4l2_dv_timings_cap *cap)
Laurent Pinchartafec5592014-01-29 10:09:41 -03001397{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001398 struct adv76xx_state *state = to_state(sd);
Laurent Pinchart7515e092014-01-31 08:51:18 -03001399
1400 if (cap->pad >= state->source_pad)
1401 return -EINVAL;
1402
Laurent Pinchartafec5592014-01-29 10:09:41 -03001403 cap->type = V4L2_DV_BT_656_1120;
1404 cap->bt.max_width = 1920;
1405 cap->bt.max_height = 1200;
1406 cap->bt.min_pixelclock = 25000000;
1407
Laurent Pinchart7515e092014-01-31 08:51:18 -03001408 switch (cap->pad) {
Pablo Antonb44b2e02015-02-03 14:13:18 -03001409 case ADV76XX_PAD_HDMI_PORT_A:
Laurent Pinchartafec5592014-01-29 10:09:41 -03001410 case ADV7604_PAD_HDMI_PORT_B:
1411 case ADV7604_PAD_HDMI_PORT_C:
1412 case ADV7604_PAD_HDMI_PORT_D:
1413 cap->bt.max_pixelclock = 225000000;
1414 break;
1415 case ADV7604_PAD_VGA_RGB:
1416 case ADV7604_PAD_VGA_COMP:
1417 default:
1418 cap->bt.max_pixelclock = 170000000;
1419 break;
1420 }
1421
1422 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1423 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1424 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1425 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1426 return 0;
1427}
1428
Hans Verkuil54450f52012-07-18 05:45:16 -03001429/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
Pablo Antonb44b2e02015-02-03 14:13:18 -03001430 if the format is listed in adv76xx_timings[] */
1431static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
Hans Verkuil54450f52012-07-18 05:45:16 -03001432 struct v4l2_dv_timings *timings)
1433{
Hans Verkuil54450f52012-07-18 05:45:16 -03001434 int i;
1435
Pablo Antonb44b2e02015-02-03 14:13:18 -03001436 for (i = 0; adv76xx_timings[i].bt.width; i++) {
1437 if (v4l2_match_dv_timings(timings, &adv76xx_timings[i],
Mats Randgaard4a31a932013-12-10 09:45:00 -03001438 is_digital_input(sd) ? 250000 : 1000000)) {
Pablo Antonb44b2e02015-02-03 14:13:18 -03001439 *timings = adv76xx_timings[i];
Hans Verkuil54450f52012-07-18 05:45:16 -03001440 break;
1441 }
1442 }
1443}
1444
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001445static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1446{
1447 unsigned int freq;
1448 int a, b;
1449
1450 a = hdmi_read(sd, 0x06);
1451 b = hdmi_read(sd, 0x3b);
1452 if (a < 0 || b < 0)
1453 return 0;
1454 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1455
1456 if (is_hdmi(sd)) {
1457 /* adjust for deep color mode */
1458 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1459
1460 freq = freq * 8 / bits_per_channel;
1461 }
1462
1463 return freq;
1464}
1465
1466static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1467{
1468 int a, b;
1469
1470 a = hdmi_read(sd, 0x51);
1471 b = hdmi_read(sd, 0x52);
1472 if (a < 0 || b < 0)
1473 return 0;
1474 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1475}
1476
Pablo Antonb44b2e02015-02-03 14:13:18 -03001477static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
Hans Verkuil54450f52012-07-18 05:45:16 -03001478 struct v4l2_dv_timings *timings)
1479{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001480 struct adv76xx_state *state = to_state(sd);
1481 const struct adv76xx_chip_info *info = state->info;
Hans Verkuil54450f52012-07-18 05:45:16 -03001482 struct v4l2_bt_timings *bt = &timings->bt;
1483 struct stdi_readback stdi;
1484
1485 if (!timings)
1486 return -EINVAL;
1487
1488 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1489
1490 if (no_signal(sd)) {
Martin Bugge1e0b9152013-12-05 10:34:46 -03001491 state->restart_stdi_once = true;
Hans Verkuil54450f52012-07-18 05:45:16 -03001492 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1493 return -ENOLINK;
1494 }
1495
1496 /* read STDI */
1497 if (read_stdi(sd, &stdi)) {
1498 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1499 return -ENOLINK;
1500 }
1501 bt->interlaced = stdi.interlaced ?
1502 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1503
Mats Randgaard4a31a932013-12-10 09:45:00 -03001504 if (is_digital_input(sd)) {
Hans Verkuil54450f52012-07-18 05:45:16 -03001505 timings->type = V4L2_DV_BT_656_1120;
1506
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001507 /* FIXME: All masks are incorrect for ADV7611 */
Laurent Pinchart51182a92014-01-08 19:30:37 -03001508 bt->width = hdmi_read16(sd, 0x07, 0xfff);
1509 bt->height = hdmi_read16(sd, 0x09, 0xfff);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001510 bt->pixelclock = info->read_hdmi_pixelclock(sd);
Laurent Pinchart51182a92014-01-08 19:30:37 -03001511 bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff);
1512 bt->hsync = hdmi_read16(sd, 0x22, 0x3ff);
1513 bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff);
1514 bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2;
1515 bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2;
1516 bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2;
Hans Verkuil54450f52012-07-18 05:45:16 -03001517 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1518 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1519 if (bt->interlaced == V4L2_DV_INTERLACED) {
Laurent Pinchart51182a92014-01-08 19:30:37 -03001520 bt->height += hdmi_read16(sd, 0x0b, 0xfff);
1521 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2;
1522 bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;
Hans Verkuilf8789e62014-09-20 07:36:39 -03001523 bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;
Hans Verkuil54450f52012-07-18 05:45:16 -03001524 }
Pablo Antonb44b2e02015-02-03 14:13:18 -03001525 adv76xx_fill_optional_dv_timings_fields(sd, timings);
Hans Verkuil54450f52012-07-18 05:45:16 -03001526 } else {
1527 /* find format
Hans Verkuil80939642012-10-16 05:46:21 -03001528 * Since LCVS values are inaccurate [REF_03, p. 275-276],
Hans Verkuil54450f52012-07-18 05:45:16 -03001529 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1530 */
1531 if (!stdi2dv_timings(sd, &stdi, timings))
1532 goto found;
1533 stdi.lcvs += 1;
1534 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1535 if (!stdi2dv_timings(sd, &stdi, timings))
1536 goto found;
1537 stdi.lcvs -= 2;
1538 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1539 if (stdi2dv_timings(sd, &stdi, timings)) {
Hans Verkuilcf9afb12012-10-16 10:12:55 -03001540 /*
1541 * The STDI block may measure wrong values, especially
1542 * for lcvs and lcf. If the driver can not find any
1543 * valid timing, the STDI block is restarted to measure
1544 * the video timings again. The function will return an
1545 * error, but the restart of STDI will generate a new
1546 * STDI interrupt and the format detection process will
1547 * restart.
1548 */
1549 if (state->restart_stdi_once) {
1550 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1551 /* TODO restart STDI for Sync Channel 2 */
1552 /* enter one-shot mode */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001553 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
Hans Verkuilcf9afb12012-10-16 10:12:55 -03001554 /* trigger STDI restart */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001555 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
Hans Verkuilcf9afb12012-10-16 10:12:55 -03001556 /* reset to continuous mode */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001557 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
Hans Verkuilcf9afb12012-10-16 10:12:55 -03001558 state->restart_stdi_once = false;
1559 return -ENOLINK;
1560 }
Hans Verkuil54450f52012-07-18 05:45:16 -03001561 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1562 return -ERANGE;
1563 }
Hans Verkuilcf9afb12012-10-16 10:12:55 -03001564 state->restart_stdi_once = true;
Hans Verkuil54450f52012-07-18 05:45:16 -03001565 }
1566found:
1567
1568 if (no_signal(sd)) {
1569 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1570 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1571 return -ENOLINK;
1572 }
1573
Mats Randgaard4a31a932013-12-10 09:45:00 -03001574 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1575 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
Hans Verkuil54450f52012-07-18 05:45:16 -03001576 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1577 __func__, (u32)bt->pixelclock);
1578 return -ERANGE;
1579 }
1580
1581 if (debug > 1)
Pablo Antonb44b2e02015-02-03 14:13:18 -03001582 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
Hans Verkuil11d034c2013-08-15 08:05:59 -03001583 timings, true);
Hans Verkuil54450f52012-07-18 05:45:16 -03001584
1585 return 0;
1586}
1587
Pablo Antonb44b2e02015-02-03 14:13:18 -03001588static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
Hans Verkuil54450f52012-07-18 05:45:16 -03001589 struct v4l2_dv_timings *timings)
1590{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001591 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -03001592 struct v4l2_bt_timings *bt;
Hans Verkuilccbd5bc2012-10-16 10:02:05 -03001593 int err;
Hans Verkuil54450f52012-07-18 05:45:16 -03001594
1595 if (!timings)
1596 return -EINVAL;
1597
Mats Randgaardd48eb482013-12-12 10:13:35 -03001598 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1599 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1600 return 0;
1601 }
1602
Hans Verkuil54450f52012-07-18 05:45:16 -03001603 bt = &timings->bt;
1604
Mats Randgaard4a31a932013-12-10 09:45:00 -03001605 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1606 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
Hans Verkuil54450f52012-07-18 05:45:16 -03001607 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1608 __func__, (u32)bt->pixelclock);
1609 return -ERANGE;
1610 }
Hans Verkuilccbd5bc2012-10-16 10:02:05 -03001611
Pablo Antonb44b2e02015-02-03 14:13:18 -03001612 adv76xx_fill_optional_dv_timings_fields(sd, timings);
Hans Verkuil54450f52012-07-18 05:45:16 -03001613
1614 state->timings = *timings;
1615
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001616 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
Hans Verkuilccbd5bc2012-10-16 10:02:05 -03001617
1618 /* Use prim_mode and vid_std when available */
1619 err = configure_predefined_video_timings(sd, timings);
1620 if (err) {
1621 /* custom settings when the video format
1622 does not have prim_mode/vid_std */
1623 configure_custom_video_timings(sd, bt);
1624 }
Hans Verkuil54450f52012-07-18 05:45:16 -03001625
1626 set_rgb_quantization_range(sd);
1627
Hans Verkuil54450f52012-07-18 05:45:16 -03001628 if (debug > 1)
Pablo Antonb44b2e02015-02-03 14:13:18 -03001629 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
Hans Verkuil11d034c2013-08-15 08:05:59 -03001630 timings, true);
Hans Verkuil54450f52012-07-18 05:45:16 -03001631 return 0;
1632}
1633
Pablo Antonb44b2e02015-02-03 14:13:18 -03001634static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
Hans Verkuil54450f52012-07-18 05:45:16 -03001635 struct v4l2_dv_timings *timings)
1636{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001637 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -03001638
1639 *timings = state->timings;
1640 return 0;
1641}
1642
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001643static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1644{
1645 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1646}
1647
1648static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1649{
1650 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1651}
1652
Hans Verkuil6b0d5d32012-10-16 06:40:45 -03001653static void enable_input(struct v4l2_subdev *sd)
Hans Verkuil54450f52012-07-18 05:45:16 -03001654{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001655 struct adv76xx_state *state = to_state(sd);
Hans Verkuil6b0d5d32012-10-16 06:40:45 -03001656
Mats Randgaard4a31a932013-12-10 09:45:00 -03001657 if (is_analog_input(sd)) {
Hans Verkuil54450f52012-07-18 05:45:16 -03001658 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
Mats Randgaard4a31a932013-12-10 09:45:00 -03001659 } else if (is_digital_input(sd)) {
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001660 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001661 state->info->set_termination(sd, true);
Hans Verkuil54450f52012-07-18 05:45:16 -03001662 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001663 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
Mats Randgaard4a31a932013-12-10 09:45:00 -03001664 } else {
1665 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1666 __func__, state->selected_input);
Hans Verkuil54450f52012-07-18 05:45:16 -03001667 }
1668}
1669
1670static void disable_input(struct v4l2_subdev *sd)
1671{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001672 struct adv76xx_state *state = to_state(sd);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001673
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001674 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
Mats Randgaard5474b982013-12-05 10:33:41 -03001675 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
Hans Verkuil54450f52012-07-18 05:45:16 -03001676 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001677 state->info->set_termination(sd, false);
Hans Verkuil54450f52012-07-18 05:45:16 -03001678}
1679
Hans Verkuil6b0d5d32012-10-16 06:40:45 -03001680static void select_input(struct v4l2_subdev *sd)
Hans Verkuil54450f52012-07-18 05:45:16 -03001681{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001682 struct adv76xx_state *state = to_state(sd);
1683 const struct adv76xx_chip_info *info = state->info;
Hans Verkuil54450f52012-07-18 05:45:16 -03001684
Mats Randgaard4a31a932013-12-10 09:45:00 -03001685 if (is_analog_input(sd)) {
Pablo Antonb44b2e02015-02-03 14:13:18 -03001686 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
Hans Verkuil54450f52012-07-18 05:45:16 -03001687
1688 afe_write(sd, 0x00, 0x08); /* power up ADC */
1689 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1690 afe_write(sd, 0xc8, 0x00); /* phase control */
Mats Randgaard4a31a932013-12-10 09:45:00 -03001691 } else if (is_digital_input(sd)) {
1692 hdmi_write(sd, 0x00, state->selected_input & 0x03);
Hans Verkuil54450f52012-07-18 05:45:16 -03001693
Pablo Antonb44b2e02015-02-03 14:13:18 -03001694 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
Hans Verkuil54450f52012-07-18 05:45:16 -03001695
Pablo Antonb44b2e02015-02-03 14:13:18 -03001696 if (adv76xx_has_afe(state)) {
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001697 afe_write(sd, 0x00, 0xff); /* power down ADC */
1698 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1699 afe_write(sd, 0xc8, 0x40); /* phase control */
1700 }
Hans Verkuil54450f52012-07-18 05:45:16 -03001701
Hans Verkuil54450f52012-07-18 05:45:16 -03001702 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1703 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1704 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
Mats Randgaard4a31a932013-12-10 09:45:00 -03001705 } else {
1706 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1707 __func__, state->selected_input);
Hans Verkuil54450f52012-07-18 05:45:16 -03001708 }
1709}
1710
Pablo Antonb44b2e02015-02-03 14:13:18 -03001711static int adv76xx_s_routing(struct v4l2_subdev *sd,
Hans Verkuil54450f52012-07-18 05:45:16 -03001712 u32 input, u32 output, u32 config)
1713{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001714 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -03001715
Mats Randgaardff4f80f2013-12-05 10:24:05 -03001716 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1717 __func__, input, state->selected_input);
1718
1719 if (input == state->selected_input)
1720 return 0;
Hans Verkuil54450f52012-07-18 05:45:16 -03001721
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001722 if (input > state->info->max_port)
1723 return -EINVAL;
1724
Mats Randgaard4a31a932013-12-10 09:45:00 -03001725 state->selected_input = input;
Hans Verkuil54450f52012-07-18 05:45:16 -03001726
1727 disable_input(sd);
1728
Hans Verkuil6b0d5d32012-10-16 06:40:45 -03001729 select_input(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -03001730
Hans Verkuil6b0d5d32012-10-16 06:40:45 -03001731 enable_input(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -03001732
1733 return 0;
1734}
1735
Pablo Antonb44b2e02015-02-03 14:13:18 -03001736static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001737 struct v4l2_subdev_fh *fh,
1738 struct v4l2_subdev_mbus_code_enum *code)
Hans Verkuil54450f52012-07-18 05:45:16 -03001739{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001740 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -03001741
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001742 if (code->index >= state->info->nformats)
1743 return -EINVAL;
1744
1745 code->code = state->info->formats[code->index].code;
1746
1747 return 0;
1748}
1749
Pablo Antonb44b2e02015-02-03 14:13:18 -03001750static void adv76xx_fill_format(struct adv76xx_state *state,
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001751 struct v4l2_mbus_framefmt *format)
1752{
1753 memset(format, 0, sizeof(*format));
1754
1755 format->width = state->timings.bt.width;
1756 format->height = state->timings.bt.height;
1757 format->field = V4L2_FIELD_NONE;
1758
1759 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861)
1760 format->colorspace = (state->timings.bt.height <= 576) ?
Hans Verkuil54450f52012-07-18 05:45:16 -03001761 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001762}
1763
1764/*
1765 * Compute the op_ch_sel value required to obtain on the bus the component order
1766 * corresponding to the selected format taking into account bus reordering
1767 * applied by the board at the output of the device.
1768 *
1769 * The following table gives the op_ch_value from the format component order
1770 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
Pablo Antonb44b2e02015-02-03 14:13:18 -03001771 * adv76xx_bus_order value in row).
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001772 *
1773 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1774 * ----------+-------------------------------------------------
1775 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1776 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1777 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1778 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1779 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1780 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1781 */
Pablo Antonb44b2e02015-02-03 14:13:18 -03001782static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001783{
1784#define _SEL(a,b,c,d,e,f) { \
Pablo Antonb44b2e02015-02-03 14:13:18 -03001785 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1786 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001787#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1788
1789 static const unsigned int op_ch_sel[6][6] = {
1790 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1791 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1792 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1793 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1794 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1795 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1796 };
1797
1798 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1799}
1800
Pablo Antonb44b2e02015-02-03 14:13:18 -03001801static void adv76xx_setup_format(struct adv76xx_state *state)
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001802{
1803 struct v4l2_subdev *sd = &state->sd;
1804
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001805 io_write_clr_set(sd, 0x02, 0x02,
Pablo Antonb44b2e02015-02-03 14:13:18 -03001806 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001807 io_write(sd, 0x03, state->format->op_format_sel |
1808 state->pdata.op_format_mode_sel);
Pablo Antonb44b2e02015-02-03 14:13:18 -03001809 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
Laurent Pinchart22d97e52014-01-30 17:17:42 -03001810 io_write_clr_set(sd, 0x05, 0x01,
Pablo Antonb44b2e02015-02-03 14:13:18 -03001811 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001812}
1813
Pablo Antonb44b2e02015-02-03 14:13:18 -03001814static int adv76xx_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001815 struct v4l2_subdev_format *format)
1816{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001817 struct adv76xx_state *state = to_state(sd);
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001818
1819 if (format->pad != state->source_pad)
1820 return -EINVAL;
1821
Pablo Antonb44b2e02015-02-03 14:13:18 -03001822 adv76xx_fill_format(state, &format->format);
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001823
1824 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1825 struct v4l2_mbus_framefmt *fmt;
1826
1827 fmt = v4l2_subdev_get_try_format(fh, format->pad);
1828 format->format.code = fmt->code;
1829 } else {
1830 format->format.code = state->format->code;
Hans Verkuil54450f52012-07-18 05:45:16 -03001831 }
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001832
1833 return 0;
1834}
1835
Pablo Antonb44b2e02015-02-03 14:13:18 -03001836static int adv76xx_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001837 struct v4l2_subdev_format *format)
1838{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001839 struct adv76xx_state *state = to_state(sd);
1840 const struct adv76xx_format_info *info;
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001841
1842 if (format->pad != state->source_pad)
1843 return -EINVAL;
1844
Pablo Antonb44b2e02015-02-03 14:13:18 -03001845 info = adv76xx_format_info(state, format->format.code);
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001846 if (info == NULL)
Pablo Antonb44b2e02015-02-03 14:13:18 -03001847 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001848
Pablo Antonb44b2e02015-02-03 14:13:18 -03001849 adv76xx_fill_format(state, &format->format);
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001850 format->format.code = info->code;
1851
1852 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1853 struct v4l2_mbus_framefmt *fmt;
1854
1855 fmt = v4l2_subdev_get_try_format(fh, format->pad);
1856 fmt->code = format->format.code;
1857 } else {
1858 state->format = info;
Pablo Antonb44b2e02015-02-03 14:13:18 -03001859 adv76xx_setup_format(state);
Laurent Pinchart539b33b2014-01-26 18:42:37 -03001860 }
1861
Hans Verkuil54450f52012-07-18 05:45:16 -03001862 return 0;
1863}
1864
Pablo Antonb44b2e02015-02-03 14:13:18 -03001865static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
Hans Verkuil54450f52012-07-18 05:45:16 -03001866{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001867 struct adv76xx_state *state = to_state(sd);
1868 const struct adv76xx_chip_info *info = state->info;
Mats Randgaardf24d2292013-12-10 10:15:13 -03001869 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1870 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1871 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1872 u8 fmt_change_digital;
1873 u8 fmt_change;
1874 u8 tx_5v;
1875
1876 if (irq_reg_0x43)
1877 io_write(sd, 0x44, irq_reg_0x43);
1878 if (irq_reg_0x70)
1879 io_write(sd, 0x71, irq_reg_0x70);
1880 if (irq_reg_0x6b)
1881 io_write(sd, 0x6c, irq_reg_0x6b);
Hans Verkuil54450f52012-07-18 05:45:16 -03001882
Mats Randgaardff4f80f2013-12-05 10:24:05 -03001883 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1884
Hans Verkuil54450f52012-07-18 05:45:16 -03001885 /* format change */
Mats Randgaardf24d2292013-12-10 10:15:13 -03001886 fmt_change = irq_reg_0x43 & 0x98;
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001887 fmt_change_digital = is_digital_input(sd)
1888 ? irq_reg_0x6b & info->fmt_change_digital_mask
1889 : 0;
Mats Randgaard14d03232013-12-05 10:26:11 -03001890
Hans Verkuil54450f52012-07-18 05:45:16 -03001891 if (fmt_change || fmt_change_digital) {
1892 v4l2_dbg(1, debug, sd,
Mats Randgaard25a64ac2013-08-14 07:58:45 -03001893 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
Hans Verkuil54450f52012-07-18 05:45:16 -03001894 __func__, fmt_change, fmt_change_digital);
Mats Randgaard25a64ac2013-08-14 07:58:45 -03001895
Pablo Antonb44b2e02015-02-03 14:13:18 -03001896 v4l2_subdev_notify(sd, ADV76XX_FMT_CHANGE, NULL);
Mats Randgaard25a64ac2013-08-14 07:58:45 -03001897
Hans Verkuil54450f52012-07-18 05:45:16 -03001898 if (handled)
1899 *handled = true;
1900 }
Mats Randgaardf24d2292013-12-10 10:15:13 -03001901 /* HDMI/DVI mode */
1902 if (irq_reg_0x6b & 0x01) {
1903 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1904 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1905 set_rgb_quantization_range(sd);
1906 if (handled)
1907 *handled = true;
1908 }
1909
Hans Verkuil54450f52012-07-18 05:45:16 -03001910 /* tx 5v detect */
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03001911 tx_5v = io_read(sd, 0x70) & info->cable_det_mask;
Hans Verkuil54450f52012-07-18 05:45:16 -03001912 if (tx_5v) {
1913 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1914 io_write(sd, 0x71, tx_5v);
Pablo Antonb44b2e02015-02-03 14:13:18 -03001915 adv76xx_s_detect_tx_5v_ctrl(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -03001916 if (handled)
1917 *handled = true;
1918 }
1919 return 0;
1920}
1921
Pablo Antonb44b2e02015-02-03 14:13:18 -03001922static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
Hans Verkuil54450f52012-07-18 05:45:16 -03001923{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001924 struct adv76xx_state *state = to_state(sd);
Mats Randgaard4a31a932013-12-10 09:45:00 -03001925 u8 *data = NULL;
Hans Verkuil54450f52012-07-18 05:45:16 -03001926
Hans Verkuildd9ac112014-11-07 09:34:57 -03001927 memset(edid->reserved, 0, sizeof(edid->reserved));
Mats Randgaard4a31a932013-12-10 09:45:00 -03001928
1929 switch (edid->pad) {
Pablo Antonb44b2e02015-02-03 14:13:18 -03001930 case ADV76XX_PAD_HDMI_PORT_A:
Laurent Pinchartc784b1e2014-01-29 10:08:58 -03001931 case ADV7604_PAD_HDMI_PORT_B:
1932 case ADV7604_PAD_HDMI_PORT_C:
1933 case ADV7604_PAD_HDMI_PORT_D:
Mats Randgaard4a31a932013-12-10 09:45:00 -03001934 if (state->edid.present & (1 << edid->pad))
1935 data = state->edid.edid;
1936 break;
1937 default:
1938 return -EINVAL;
Mats Randgaard4a31a932013-12-10 09:45:00 -03001939 }
Hans Verkuildd9ac112014-11-07 09:34:57 -03001940
1941 if (edid->start_block == 0 && edid->blocks == 0) {
1942 edid->blocks = data ? state->edid.blocks : 0;
1943 return 0;
1944 }
1945
1946 if (data == NULL)
Mats Randgaard4a31a932013-12-10 09:45:00 -03001947 return -ENODATA;
1948
Hans Verkuildd9ac112014-11-07 09:34:57 -03001949 if (edid->start_block >= state->edid.blocks)
1950 return -EINVAL;
1951
1952 if (edid->start_block + edid->blocks > state->edid.blocks)
1953 edid->blocks = state->edid.blocks - edid->start_block;
1954
1955 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
1956
Hans Verkuil54450f52012-07-18 05:45:16 -03001957 return 0;
1958}
1959
Mats Randgaarddd08beb2013-12-10 09:57:09 -03001960static int get_edid_spa_location(const u8 *edid)
Mats Randgaard3e86aa82013-12-10 09:55:18 -03001961{
1962 u8 d;
1963
1964 if ((edid[0x7e] != 1) ||
1965 (edid[0x80] != 0x02) ||
1966 (edid[0x81] != 0x03)) {
1967 return -1;
1968 }
1969
1970 /* search Vendor Specific Data Block (tag 3) */
1971 d = edid[0x82] & 0x7f;
1972 if (d > 4) {
1973 int i = 0x84;
1974 int end = 0x80 + d;
1975
1976 do {
1977 u8 tag = edid[i] >> 5;
1978 u8 len = edid[i] & 0x1f;
1979
1980 if ((tag == 3) && (len >= 5))
1981 return i + 4;
1982 i += len + 1;
1983 } while (i < end);
1984 }
1985 return -1;
1986}
1987
Pablo Antonb44b2e02015-02-03 14:13:18 -03001988static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
Hans Verkuil54450f52012-07-18 05:45:16 -03001989{
Pablo Antonb44b2e02015-02-03 14:13:18 -03001990 struct adv76xx_state *state = to_state(sd);
1991 const struct adv76xx_chip_info *info = state->info;
Mats Randgaarddd08beb2013-12-10 09:57:09 -03001992 int spa_loc;
Hans Verkuil54450f52012-07-18 05:45:16 -03001993 int err;
Mats Randgaarddd08beb2013-12-10 09:57:09 -03001994 int i;
Hans Verkuil54450f52012-07-18 05:45:16 -03001995
Hans Verkuildd9ac112014-11-07 09:34:57 -03001996 memset(edid->reserved, 0, sizeof(edid->reserved));
1997
Laurent Pinchartc784b1e2014-01-29 10:08:58 -03001998 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
Hans Verkuil54450f52012-07-18 05:45:16 -03001999 return -EINVAL;
2000 if (edid->start_block != 0)
2001 return -EINVAL;
2002 if (edid->blocks == 0) {
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002003 /* Disable hotplug and I2C access to EDID RAM from DDC port */
Mats Randgaard4a31a932013-12-10 09:45:00 -03002004 state->edid.present &= ~(1 << edid->pad);
Pablo Antonb44b2e02015-02-03 14:13:18 -03002005 adv76xx_set_hpd(state, state->edid.present);
Laurent Pinchart22d97e52014-01-30 17:17:42 -03002006 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002007
Hans Verkuil54450f52012-07-18 05:45:16 -03002008 /* Fall back to a 16:9 aspect ratio */
2009 state->aspect_ratio.numerator = 16;
2010 state->aspect_ratio.denominator = 9;
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002011
2012 if (!state->edid.present)
2013 state->edid.blocks = 0;
2014
2015 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2016 __func__, edid->pad, state->edid.present);
Hans Verkuil54450f52012-07-18 05:45:16 -03002017 return 0;
2018 }
Mats Randgaard4a31a932013-12-10 09:45:00 -03002019 if (edid->blocks > 2) {
2020 edid->blocks = 2;
Hans Verkuil54450f52012-07-18 05:45:16 -03002021 return -E2BIG;
Mats Randgaard4a31a932013-12-10 09:45:00 -03002022 }
Mats Randgaard4a31a932013-12-10 09:45:00 -03002023
Mats Randgaarddd08beb2013-12-10 09:57:09 -03002024 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2025 __func__, edid->pad, state->edid.present);
2026
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002027 /* Disable hotplug and I2C access to EDID RAM from DDC port */
Mats Randgaard4a31a932013-12-10 09:45:00 -03002028 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
Pablo Antonb44b2e02015-02-03 14:13:18 -03002029 adv76xx_set_hpd(state, 0);
Laurent Pinchart22d97e52014-01-30 17:17:42 -03002030 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002031
Mats Randgaarddd08beb2013-12-10 09:57:09 -03002032 spa_loc = get_edid_spa_location(edid->edid);
2033 if (spa_loc < 0)
2034 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2035
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002036 switch (edid->pad) {
Pablo Antonb44b2e02015-02-03 14:13:18 -03002037 case ADV76XX_PAD_HDMI_PORT_A:
Mats Randgaarddd08beb2013-12-10 09:57:09 -03002038 state->spa_port_a[0] = edid->edid[spa_loc];
2039 state->spa_port_a[1] = edid->edid[spa_loc + 1];
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002040 break;
Laurent Pinchartc784b1e2014-01-29 10:08:58 -03002041 case ADV7604_PAD_HDMI_PORT_B:
Mats Randgaarddd08beb2013-12-10 09:57:09 -03002042 rep_write(sd, 0x70, edid->edid[spa_loc]);
2043 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002044 break;
Laurent Pinchartc784b1e2014-01-29 10:08:58 -03002045 case ADV7604_PAD_HDMI_PORT_C:
Mats Randgaarddd08beb2013-12-10 09:57:09 -03002046 rep_write(sd, 0x72, edid->edid[spa_loc]);
2047 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002048 break;
Laurent Pinchartc784b1e2014-01-29 10:08:58 -03002049 case ADV7604_PAD_HDMI_PORT_D:
Mats Randgaarddd08beb2013-12-10 09:57:09 -03002050 rep_write(sd, 0x74, edid->edid[spa_loc]);
2051 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002052 break;
Mats Randgaarddd08beb2013-12-10 09:57:09 -03002053 default:
2054 return -EINVAL;
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002055 }
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002056
2057 if (info->type == ADV7604) {
2058 rep_write(sd, 0x76, spa_loc & 0xff);
Laurent Pinchart22d97e52014-01-30 17:17:42 -03002059 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002060 } else {
2061 /* FIXME: Where is the SPA location LSB register ? */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03002062 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002063 }
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002064
Mats Randgaarddd08beb2013-12-10 09:57:09 -03002065 edid->edid[spa_loc] = state->spa_port_a[0];
2066 edid->edid[spa_loc + 1] = state->spa_port_a[1];
Mats Randgaard4a31a932013-12-10 09:45:00 -03002067
2068 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2069 state->edid.blocks = edid->blocks;
Hans Verkuil54450f52012-07-18 05:45:16 -03002070 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2071 edid->edid[0x16]);
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002072 state->edid.present |= 1 << edid->pad;
Mats Randgaard4a31a932013-12-10 09:45:00 -03002073
2074 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2075 if (err < 0) {
Mats Randgaard3e86aa82013-12-10 09:55:18 -03002076 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
Mats Randgaard4a31a932013-12-10 09:45:00 -03002077 return err;
2078 }
2079
Pablo Antonb44b2e02015-02-03 14:13:18 -03002080 /* adv76xx calculates the checksums and enables I2C access to internal
Mats Randgaarddd08beb2013-12-10 09:57:09 -03002081 EDID RAM from DDC port. */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03002082 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
Mats Randgaarddd08beb2013-12-10 09:57:09 -03002083
2084 for (i = 0; i < 1000; i++) {
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002085 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
Mats Randgaarddd08beb2013-12-10 09:57:09 -03002086 break;
2087 mdelay(1);
2088 }
2089 if (i == 1000) {
2090 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2091 return -EIO;
2092 }
2093
Mats Randgaard4a31a932013-12-10 09:45:00 -03002094 /* enable hotplug after 100 ms */
2095 queue_delayed_work(state->work_queues,
2096 &state->delayed_work_enable_hotplug, HZ / 10);
2097 return 0;
Hans Verkuil54450f52012-07-18 05:45:16 -03002098}
2099
2100/*********** avi info frame CEA-861-E **************/
2101
2102static void print_avi_infoframe(struct v4l2_subdev *sd)
2103{
2104 int i;
2105 u8 buf[14];
2106 u8 avi_len;
2107 u8 avi_ver;
2108
Martin Buggebb88f322013-08-14 08:52:46 -03002109 if (!is_hdmi(sd)) {
Hans Verkuil54450f52012-07-18 05:45:16 -03002110 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2111 return;
2112 }
2113 if (!(io_read(sd, 0x60) & 0x01)) {
2114 v4l2_info(sd, "AVI infoframe not received\n");
2115 return;
2116 }
2117
2118 if (io_read(sd, 0x83) & 0x01) {
2119 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
2120 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2121 if (io_read(sd, 0x83) & 0x01) {
2122 v4l2_info(sd, "AVI infoframe checksum error still present\n");
2123 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2124 }
2125 }
2126
2127 avi_len = infoframe_read(sd, 0xe2);
2128 avi_ver = infoframe_read(sd, 0xe1);
2129 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2130 avi_ver, avi_len);
2131
2132 if (avi_ver != 0x02)
2133 return;
2134
2135 for (i = 0; i < 14; i++)
2136 buf[i] = infoframe_read(sd, i);
2137
2138 v4l2_info(sd,
2139 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2140 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2141 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2142}
2143
Pablo Antonb44b2e02015-02-03 14:13:18 -03002144static int adv76xx_log_status(struct v4l2_subdev *sd)
Hans Verkuil54450f52012-07-18 05:45:16 -03002145{
Pablo Antonb44b2e02015-02-03 14:13:18 -03002146 struct adv76xx_state *state = to_state(sd);
2147 const struct adv76xx_chip_info *info = state->info;
Hans Verkuil54450f52012-07-18 05:45:16 -03002148 struct v4l2_dv_timings timings;
2149 struct stdi_readback stdi;
2150 u8 reg_io_0x02 = io_read(sd, 0x02);
Laurent Pinchart4a2ccdd2014-01-08 20:26:55 -03002151 u8 edid_enabled;
2152 u8 cable_det;
Hans Verkuil54450f52012-07-18 05:45:16 -03002153
Lars-Peter Clausenf216ccb2013-11-25 16:15:29 -03002154 static const char * const csc_coeff_sel_rb[16] = {
Hans Verkuil54450f52012-07-18 05:45:16 -03002155 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2156 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2157 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2158 "reserved", "reserved", "reserved", "reserved", "manual"
2159 };
Lars-Peter Clausenf216ccb2013-11-25 16:15:29 -03002160 static const char * const input_color_space_txt[16] = {
Hans Verkuil54450f52012-07-18 05:45:16 -03002161 "RGB limited range (16-235)", "RGB full range (0-255)",
2162 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
Mats Randgaard98332392013-12-05 10:05:58 -03002163 "xvYCC Bt.601", "xvYCC Bt.709",
Hans Verkuil54450f52012-07-18 05:45:16 -03002164 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2165 "invalid", "invalid", "invalid", "invalid", "invalid",
2166 "invalid", "invalid", "automatic"
2167 };
Lars-Peter Clausenf216ccb2013-11-25 16:15:29 -03002168 static const char * const rgb_quantization_range_txt[] = {
Hans Verkuil54450f52012-07-18 05:45:16 -03002169 "Automatic",
2170 "RGB limited range (16-235)",
2171 "RGB full range (0-255)",
2172 };
Lars-Peter Clausenf216ccb2013-11-25 16:15:29 -03002173 static const char * const deep_color_mode_txt[4] = {
Martin Buggebb88f322013-08-14 08:52:46 -03002174 "8-bits per channel",
2175 "10-bits per channel",
2176 "12-bits per channel",
2177 "16-bits per channel (not supported)"
2178 };
Hans Verkuil54450f52012-07-18 05:45:16 -03002179
2180 v4l2_info(sd, "-----Chip status-----\n");
2181 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002182 edid_enabled = rep_read(sd, info->edid_status_reg);
Mats Randgaard4a31a932013-12-10 09:45:00 -03002183 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
Laurent Pinchart4a2ccdd2014-01-08 20:26:55 -03002184 ((edid_enabled & 0x01) ? "Yes" : "No"),
2185 ((edid_enabled & 0x02) ? "Yes" : "No"),
2186 ((edid_enabled & 0x04) ? "Yes" : "No"),
2187 ((edid_enabled & 0x08) ? "Yes" : "No"));
Hans Verkuil54450f52012-07-18 05:45:16 -03002188 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2189 "enabled" : "disabled");
2190
2191 v4l2_info(sd, "-----Signal status-----\n");
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002192 cable_det = info->read_cable_det(sd);
Mats Randgaard4a31a932013-12-10 09:45:00 -03002193 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002194 ((cable_det & 0x01) ? "Yes" : "No"),
2195 ((cable_det & 0x02) ? "Yes" : "No"),
Laurent Pinchart4a2ccdd2014-01-08 20:26:55 -03002196 ((cable_det & 0x04) ? "Yes" : "No"),
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002197 ((cable_det & 0x08) ? "Yes" : "No"));
Hans Verkuil54450f52012-07-18 05:45:16 -03002198 v4l2_info(sd, "TMDS signal detected: %s\n",
2199 no_signal_tmds(sd) ? "false" : "true");
2200 v4l2_info(sd, "TMDS signal locked: %s\n",
2201 no_lock_tmds(sd) ? "false" : "true");
2202 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2203 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2204 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2205 v4l2_info(sd, "CP free run: %s\n",
jean-michel.hautbois@vodalys.com58514622015-02-06 11:37:58 -03002206 (in_free_run(sd)) ? "on" : "off");
Hans Verkuilccbd5bc2012-10-16 10:02:05 -03002207 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2208 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2209 (io_read(sd, 0x01) & 0x70) >> 4);
Hans Verkuil54450f52012-07-18 05:45:16 -03002210
2211 v4l2_info(sd, "-----Video Timings-----\n");
2212 if (read_stdi(sd, &stdi))
2213 v4l2_info(sd, "STDI: not locked\n");
2214 else
2215 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2216 stdi.lcf, stdi.bl, stdi.lcvs,
2217 stdi.interlaced ? "interlaced" : "progressive",
2218 stdi.hs_pol, stdi.vs_pol);
Pablo Antonb44b2e02015-02-03 14:13:18 -03002219 if (adv76xx_query_dv_timings(sd, &timings))
Hans Verkuil54450f52012-07-18 05:45:16 -03002220 v4l2_info(sd, "No video detected\n");
2221 else
Hans Verkuil11d034c2013-08-15 08:05:59 -03002222 v4l2_print_dv_timings(sd->name, "Detected format: ",
2223 &timings, true);
2224 v4l2_print_dv_timings(sd->name, "Configured format: ",
2225 &state->timings, true);
Hans Verkuil54450f52012-07-18 05:45:16 -03002226
Mats Randgaard76eb2d32013-08-14 08:56:57 -03002227 if (no_signal(sd))
2228 return 0;
2229
Hans Verkuil54450f52012-07-18 05:45:16 -03002230 v4l2_info(sd, "-----Color space-----\n");
2231 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2232 rgb_quantization_range_txt[state->rgb_quantization_range]);
2233 v4l2_info(sd, "Input color space: %s\n",
2234 input_color_space_txt[reg_io_0x02 >> 4]);
2235 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2236 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2237 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2238 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
Mats Randgaard76eb2d32013-08-14 08:56:57 -03002239 "enabled" : "disabled");
Hans Verkuil54450f52012-07-18 05:45:16 -03002240 v4l2_info(sd, "Color space conversion: %s\n",
jean-michel.hautbois@vodalys.com80f49442015-02-04 11:16:00 -03002241 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
Hans Verkuil54450f52012-07-18 05:45:16 -03002242
Mats Randgaard4a31a932013-12-10 09:45:00 -03002243 if (!is_digital_input(sd))
Mats Randgaard76eb2d32013-08-14 08:56:57 -03002244 return 0;
2245
2246 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
Mats Randgaard4a31a932013-12-10 09:45:00 -03002247 v4l2_info(sd, "Digital video port selected: %c\n",
2248 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2249 v4l2_info(sd, "HDCP encrypted content: %s\n",
2250 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
Mats Randgaard76eb2d32013-08-14 08:56:57 -03002251 v4l2_info(sd, "HDCP keys read: %s%s\n",
2252 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2253 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
Hans Verkuil77639ff2014-09-12 06:02:02 -03002254 if (is_hdmi(sd)) {
Mats Randgaard76eb2d32013-08-14 08:56:57 -03002255 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2256 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2257 bool audio_mute = io_read(sd, 0x65) & 0x40;
2258
2259 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2260 audio_pll_locked ? "locked" : "not locked",
2261 audio_sample_packet_detect ? "detected" : "not detected",
2262 audio_mute ? "muted" : "enabled");
2263 if (audio_pll_locked && audio_sample_packet_detect) {
2264 v4l2_info(sd, "Audio format: %s\n",
2265 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2266 }
2267 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2268 (hdmi_read(sd, 0x5c) << 8) +
2269 (hdmi_read(sd, 0x5d) & 0xf0));
2270 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2271 (hdmi_read(sd, 0x5e) << 8) +
2272 hdmi_read(sd, 0x5f));
2273 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2274
2275 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2276
Hans Verkuil54450f52012-07-18 05:45:16 -03002277 print_avi_infoframe(sd);
2278 }
2279
2280 return 0;
2281}
2282
2283/* ----------------------------------------------------------------------- */
2284
Pablo Antonb44b2e02015-02-03 14:13:18 -03002285static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2286 .s_ctrl = adv76xx_s_ctrl,
Hans Verkuil54450f52012-07-18 05:45:16 -03002287};
2288
Pablo Antonb44b2e02015-02-03 14:13:18 -03002289static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2290 .log_status = adv76xx_log_status,
2291 .interrupt_service_routine = adv76xx_isr,
Hans Verkuil54450f52012-07-18 05:45:16 -03002292#ifdef CONFIG_VIDEO_ADV_DEBUG
Pablo Antonb44b2e02015-02-03 14:13:18 -03002293 .g_register = adv76xx_g_register,
2294 .s_register = adv76xx_s_register,
Hans Verkuil54450f52012-07-18 05:45:16 -03002295#endif
2296};
2297
Pablo Antonb44b2e02015-02-03 14:13:18 -03002298static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2299 .s_routing = adv76xx_s_routing,
2300 .g_input_status = adv76xx_g_input_status,
2301 .s_dv_timings = adv76xx_s_dv_timings,
2302 .g_dv_timings = adv76xx_g_dv_timings,
2303 .query_dv_timings = adv76xx_query_dv_timings,
Hans Verkuil54450f52012-07-18 05:45:16 -03002304};
2305
Pablo Antonb44b2e02015-02-03 14:13:18 -03002306static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2307 .enum_mbus_code = adv76xx_enum_mbus_code,
2308 .get_fmt = adv76xx_get_format,
2309 .set_fmt = adv76xx_set_format,
2310 .get_edid = adv76xx_get_edid,
2311 .set_edid = adv76xx_set_edid,
2312 .dv_timings_cap = adv76xx_dv_timings_cap,
2313 .enum_dv_timings = adv76xx_enum_dv_timings,
Hans Verkuil54450f52012-07-18 05:45:16 -03002314};
2315
Pablo Antonb44b2e02015-02-03 14:13:18 -03002316static const struct v4l2_subdev_ops adv76xx_ops = {
2317 .core = &adv76xx_core_ops,
2318 .video = &adv76xx_video_ops,
2319 .pad = &adv76xx_pad_ops,
Hans Verkuil54450f52012-07-18 05:45:16 -03002320};
2321
2322/* -------------------------- custom ctrls ---------------------------------- */
2323
2324static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
Pablo Antonb44b2e02015-02-03 14:13:18 -03002325 .ops = &adv76xx_ctrl_ops,
Hans Verkuil54450f52012-07-18 05:45:16 -03002326 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2327 .name = "Analog Sampling Phase",
2328 .type = V4L2_CTRL_TYPE_INTEGER,
2329 .min = 0,
2330 .max = 0x1f,
2331 .step = 1,
2332 .def = 0,
2333};
2334
Pablo Antonb44b2e02015-02-03 14:13:18 -03002335static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2336 .ops = &adv76xx_ctrl_ops,
Hans Verkuil54450f52012-07-18 05:45:16 -03002337 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2338 .name = "Free Running Color, Manual",
2339 .type = V4L2_CTRL_TYPE_BOOLEAN,
2340 .min = false,
2341 .max = true,
2342 .step = 1,
2343 .def = false,
2344};
2345
Pablo Antonb44b2e02015-02-03 14:13:18 -03002346static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2347 .ops = &adv76xx_ctrl_ops,
Hans Verkuil54450f52012-07-18 05:45:16 -03002348 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2349 .name = "Free Running Color",
2350 .type = V4L2_CTRL_TYPE_INTEGER,
2351 .min = 0x0,
2352 .max = 0xffffff,
2353 .step = 0x1,
2354 .def = 0x0,
2355};
2356
2357/* ----------------------------------------------------------------------- */
2358
Pablo Antonb44b2e02015-02-03 14:13:18 -03002359static int adv76xx_core_init(struct v4l2_subdev *sd)
Hans Verkuil54450f52012-07-18 05:45:16 -03002360{
Pablo Antonb44b2e02015-02-03 14:13:18 -03002361 struct adv76xx_state *state = to_state(sd);
2362 const struct adv76xx_chip_info *info = state->info;
2363 struct adv76xx_platform_data *pdata = &state->pdata;
Hans Verkuil54450f52012-07-18 05:45:16 -03002364
2365 hdmi_write(sd, 0x48,
2366 (pdata->disable_pwrdnb ? 0x80 : 0) |
2367 (pdata->disable_cable_det_rst ? 0x40 : 0));
2368
2369 disable_input(sd);
2370
Laurent Pinchart5ef54b52014-01-31 10:57:27 -03002371 if (pdata->default_input >= 0 &&
2372 pdata->default_input < state->source_pad) {
2373 state->selected_input = pdata->default_input;
2374 select_input(sd);
2375 enable_input(sd);
2376 }
2377
Hans Verkuil54450f52012-07-18 05:45:16 -03002378 /* power */
2379 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2380 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2381 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2382
2383 /* video format */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03002384 io_write_clr_set(sd, 0x02, 0x0f,
Hans Verkuil54450f52012-07-18 05:45:16 -03002385 pdata->alt_gamma << 3 |
2386 pdata->op_656_range << 2 |
Hans Verkuil54450f52012-07-18 05:45:16 -03002387 pdata->alt_data_sat << 0);
Laurent Pinchart22d97e52014-01-30 17:17:42 -03002388 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
Laurent Pinchart539b33b2014-01-26 18:42:37 -03002389 pdata->insert_av_codes << 2 |
2390 pdata->replicate_av_codes << 1);
Pablo Antonb44b2e02015-02-03 14:13:18 -03002391 adv76xx_setup_format(state);
Hans Verkuil54450f52012-07-18 05:45:16 -03002392
Hans Verkuil54450f52012-07-18 05:45:16 -03002393 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
Martin Bugge98908692013-12-20 05:14:57 -03002394
2395 /* VS, HS polarities */
Laurent Pinchart1b5ab872014-02-04 19:57:56 -03002396 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2397 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
Mikhail Khelikf31b62e2013-12-20 05:12:00 -03002398
2399 /* Adjust drive strength */
2400 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2401 pdata->dr_str_clk << 2 |
2402 pdata->dr_str_sync);
2403
Hans Verkuil54450f52012-07-18 05:45:16 -03002404 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2405 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2406 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
Hans Verkuil80939642012-10-16 05:46:21 -03002407 ADI recommended setting [REF_01, c. 2.3.3] */
Hans Verkuil54450f52012-07-18 05:45:16 -03002408 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
Hans Verkuil80939642012-10-16 05:46:21 -03002409 ADI recommended setting [REF_01, c. 2.3.3] */
Hans Verkuil54450f52012-07-18 05:45:16 -03002410 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2411 for digital formats */
2412
Mats Randgaard5474b982013-12-05 10:33:41 -03002413 /* HDMI audio */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03002414 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2415 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2416 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
Mats Randgaard5474b982013-12-05 10:33:41 -03002417
Hans Verkuil54450f52012-07-18 05:45:16 -03002418 /* TODO from platform data */
2419 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2420
Pablo Antonb44b2e02015-02-03 14:13:18 -03002421 if (adv76xx_has_afe(state)) {
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002422 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
Laurent Pinchart22d97e52014-01-30 17:17:42 -03002423 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002424 }
Hans Verkuil54450f52012-07-18 05:45:16 -03002425
Hans Verkuil54450f52012-07-18 05:45:16 -03002426 /* interrupts */
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002427 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
Hans Verkuil54450f52012-07-18 05:45:16 -03002428 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002429 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2430 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2431 info->setup_irqs(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -03002432
2433 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2434}
2435
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002436static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2437{
2438 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2439}
2440
2441static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2442{
2443 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2444}
2445
Pablo Antonb44b2e02015-02-03 14:13:18 -03002446static void adv76xx_unregister_clients(struct adv76xx_state *state)
Hans Verkuil54450f52012-07-18 05:45:16 -03002447{
Laurent Pinchart05cacb12014-01-30 16:32:21 -03002448 unsigned int i;
2449
2450 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2451 if (state->i2c_clients[i])
2452 i2c_unregister_device(state->i2c_clients[i]);
2453 }
Hans Verkuil54450f52012-07-18 05:45:16 -03002454}
2455
Pablo Antonb44b2e02015-02-03 14:13:18 -03002456static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
Hans Verkuil54450f52012-07-18 05:45:16 -03002457 u8 addr, u8 io_reg)
2458{
2459 struct i2c_client *client = v4l2_get_subdevdata(sd);
2460
2461 if (addr)
2462 io_write(sd, io_reg, addr << 1);
2463 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2464}
2465
Pablo Antonb44b2e02015-02-03 14:13:18 -03002466static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002467 /* reset ADI recommended settings for HDMI: */
2468 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
Pablo Antonb44b2e02015-02-03 14:13:18 -03002469 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2470 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2471 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2472 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2473 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2474 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2475 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2476 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2477 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2478 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2479 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2480 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002481
2482 /* set ADI recommended settings for digitizer */
2483 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
Pablo Antonb44b2e02015-02-03 14:13:18 -03002484 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2485 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2486 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2487 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2488 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002489
Pablo Antonb44b2e02015-02-03 14:13:18 -03002490 { ADV76XX_REG_SEQ_TERM, 0 },
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002491};
2492
Pablo Antonb44b2e02015-02-03 14:13:18 -03002493static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002494 /* set ADI recommended settings for HDMI: */
2495 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
Pablo Antonb44b2e02015-02-03 14:13:18 -03002496 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2497 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2498 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2499 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2500 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2501 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2502 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2503 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2504 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2505 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2506 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002507
2508 /* reset ADI recommended settings for digitizer */
2509 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
Pablo Antonb44b2e02015-02-03 14:13:18 -03002510 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2511 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002512
Pablo Antonb44b2e02015-02-03 14:13:18 -03002513 { ADV76XX_REG_SEQ_TERM, 0 },
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002514};
2515
Pablo Antonb44b2e02015-02-03 14:13:18 -03002516static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
Lars-Peter Clausenc41ad9c2014-06-17 08:52:24 -03002517 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
Pablo Antonb44b2e02015-02-03 14:13:18 -03002518 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2519 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2520 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2521 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2522 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2523 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2524 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2525 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2526 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2527 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2528 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002529
Pablo Antonb44b2e02015-02-03 14:13:18 -03002530 { ADV76XX_REG_SEQ_TERM, 0 },
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002531};
2532
Pablo Antonb44b2e02015-02-03 14:13:18 -03002533static const struct adv76xx_chip_info adv76xx_chip_info[] = {
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002534 [ADV7604] = {
2535 .type = ADV7604,
2536 .has_afe = true,
Laurent Pinchartc784b1e2014-01-29 10:08:58 -03002537 .max_port = ADV7604_PAD_VGA_COMP,
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002538 .num_dv_ports = 4,
2539 .edid_enable_reg = 0x77,
2540 .edid_status_reg = 0x7d,
2541 .lcf_reg = 0xb3,
2542 .tdms_lock_mask = 0xe0,
2543 .cable_det_mask = 0x1e,
2544 .fmt_change_digital_mask = 0xc1,
jean-michel.hautbois@vodalys.com80f49442015-02-04 11:16:00 -03002545 .cp_csc = 0xfc,
Laurent Pinchart539b33b2014-01-26 18:42:37 -03002546 .formats = adv7604_formats,
2547 .nformats = ARRAY_SIZE(adv7604_formats),
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002548 .set_termination = adv7604_set_termination,
2549 .setup_irqs = adv7604_setup_irqs,
2550 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2551 .read_cable_det = adv7604_read_cable_det,
2552 .recommended_settings = {
2553 [0] = adv7604_recommended_settings_afe,
2554 [1] = adv7604_recommended_settings_hdmi,
2555 },
2556 .num_recommended_settings = {
2557 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2558 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2559 },
Pablo Antonb44b2e02015-02-03 14:13:18 -03002560 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2561 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002562 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
Pablo Antonb44b2e02015-02-03 14:13:18 -03002563 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2564 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2565 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002566 BIT(ADV7604_PAGE_VDP),
2567 },
2568 [ADV7611] = {
2569 .type = ADV7611,
2570 .has_afe = false,
Pablo Antonb44b2e02015-02-03 14:13:18 -03002571 .max_port = ADV76XX_PAD_HDMI_PORT_A,
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002572 .num_dv_ports = 1,
2573 .edid_enable_reg = 0x74,
2574 .edid_status_reg = 0x76,
2575 .lcf_reg = 0xa3,
2576 .tdms_lock_mask = 0x43,
2577 .cable_det_mask = 0x01,
2578 .fmt_change_digital_mask = 0x03,
jean-michel.hautbois@vodalys.com80f49442015-02-04 11:16:00 -03002579 .cp_csc = 0xf4,
Laurent Pinchart539b33b2014-01-26 18:42:37 -03002580 .formats = adv7611_formats,
2581 .nformats = ARRAY_SIZE(adv7611_formats),
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002582 .set_termination = adv7611_set_termination,
2583 .setup_irqs = adv7611_setup_irqs,
2584 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2585 .read_cable_det = adv7611_read_cable_det,
2586 .recommended_settings = {
2587 [1] = adv7611_recommended_settings_hdmi,
2588 },
2589 .num_recommended_settings = {
2590 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2591 },
Pablo Antonb44b2e02015-02-03 14:13:18 -03002592 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2593 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2594 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2595 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002596 },
2597};
2598
Pablo Antonb44b2e02015-02-03 14:13:18 -03002599static struct i2c_device_id adv76xx_i2c_id[] = {
2600 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2601 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002602 { }
2603};
Pablo Antonb44b2e02015-02-03 14:13:18 -03002604MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002605
Pablo Antonb44b2e02015-02-03 14:13:18 -03002606static struct of_device_id adv76xx_of_id[] __maybe_unused = {
2607 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002608 { }
2609};
Pablo Antonb44b2e02015-02-03 14:13:18 -03002610MODULE_DEVICE_TABLE(of, adv76xx_of_id);
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002611
Pablo Antonb44b2e02015-02-03 14:13:18 -03002612static int adv76xx_parse_dt(struct adv76xx_state *state)
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002613{
Laurent Pinchart6fa88042014-02-04 20:23:16 -03002614 struct v4l2_of_endpoint bus_cfg;
2615 struct device_node *endpoint;
2616 struct device_node *np;
2617 unsigned int flags;
2618
Pablo Antonb44b2e02015-02-03 14:13:18 -03002619 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
Laurent Pinchart6fa88042014-02-04 20:23:16 -03002620
2621 /* Parse the endpoint. */
2622 endpoint = of_graph_get_next_endpoint(np, NULL);
2623 if (!endpoint)
2624 return -EINVAL;
2625
2626 v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2627 of_node_put(endpoint);
2628
2629 flags = bus_cfg.bus.parallel.flags;
2630
2631 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2632 state->pdata.inv_hs_pol = 1;
2633
2634 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2635 state->pdata.inv_vs_pol = 1;
2636
2637 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2638 state->pdata.inv_llc_pol = 1;
2639
2640 if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2641 state->pdata.insert_av_codes = 1;
2642 state->pdata.op_656_range = 1;
2643 }
2644
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002645 /* Disable the interrupt for now as no DT-based board uses it. */
Pablo Antonb44b2e02015-02-03 14:13:18 -03002646 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002647
2648 /* Use the default I2C addresses. */
2649 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
Pablo Antonb44b2e02015-02-03 14:13:18 -03002650 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2651 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002652 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2653 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
Pablo Antonb44b2e02015-02-03 14:13:18 -03002654 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2655 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2656 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2657 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2658 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2659 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002660 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2661
2662 /* Hardcode the remaining platform data fields. */
2663 state->pdata.disable_pwrdnb = 0;
2664 state->pdata.disable_cable_det_rst = 0;
2665 state->pdata.default_input = -1;
2666 state->pdata.blank_data = 1;
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002667 state->pdata.alt_data_sat = 1;
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002668 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2669 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2670
2671 return 0;
2672}
2673
Pablo Antonb44b2e02015-02-03 14:13:18 -03002674static int adv76xx_probe(struct i2c_client *client,
Hans Verkuil54450f52012-07-18 05:45:16 -03002675 const struct i2c_device_id *id)
2676{
Hans Verkuil591b72f2013-12-17 10:05:13 -03002677 static const struct v4l2_dv_timings cea640x480 =
2678 V4L2_DV_BT_CEA_640X480P59_94;
Pablo Antonb44b2e02015-02-03 14:13:18 -03002679 struct adv76xx_state *state;
Hans Verkuil54450f52012-07-18 05:45:16 -03002680 struct v4l2_ctrl_handler *hdl;
2681 struct v4l2_subdev *sd;
Laurent Pinchartc784b1e2014-01-29 10:08:58 -03002682 unsigned int i;
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002683 u16 val;
Hans Verkuil54450f52012-07-18 05:45:16 -03002684 int err;
2685
2686 /* Check if the adapter supports the needed features */
2687 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2688 return -EIO;
Pablo Antonb44b2e02015-02-03 14:13:18 -03002689 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
Hans Verkuil54450f52012-07-18 05:45:16 -03002690 client->addr << 1);
2691
Laurent Pinchartc02b2112013-05-02 08:29:43 -03002692 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
Hans Verkuil54450f52012-07-18 05:45:16 -03002693 if (!state) {
Pablo Antonb44b2e02015-02-03 14:13:18 -03002694 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
Hans Verkuil54450f52012-07-18 05:45:16 -03002695 return -ENOMEM;
2696 }
2697
Pablo Antonb44b2e02015-02-03 14:13:18 -03002698 state->i2c_clients[ADV76XX_PAGE_IO] = client;
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002699
Mats Randgaard25a64ac2013-08-14 07:58:45 -03002700 /* initialize variables */
2701 state->restart_stdi_once = true;
Mats Randgaardff4f80f2013-12-05 10:24:05 -03002702 state->selected_input = ~0;
Mats Randgaard25a64ac2013-08-14 07:58:45 -03002703
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002704 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2705 const struct of_device_id *oid;
2706
Pablo Antonb44b2e02015-02-03 14:13:18 -03002707 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002708 state->info = oid->data;
2709
Pablo Antonb44b2e02015-02-03 14:13:18 -03002710 err = adv76xx_parse_dt(state);
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002711 if (err < 0) {
2712 v4l_err(client, "DT parsing error\n");
2713 return err;
2714 }
2715 } else if (client->dev.platform_data) {
Pablo Antonb44b2e02015-02-03 14:13:18 -03002716 struct adv76xx_platform_data *pdata = client->dev.platform_data;
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002717
Pablo Antonb44b2e02015-02-03 14:13:18 -03002718 state->info = (const struct adv76xx_chip_info *)id->driver_data;
Laurent Pinchartf82f3132013-11-25 16:19:08 -03002719 state->pdata = *pdata;
2720 } else {
Hans Verkuil54450f52012-07-18 05:45:16 -03002721 v4l_err(client, "No platform data!\n");
Laurent Pinchartc02b2112013-05-02 08:29:43 -03002722 return -ENODEV;
Hans Verkuil54450f52012-07-18 05:45:16 -03002723 }
Laurent Pincharte9d50e92014-01-30 18:37:08 -03002724
2725 /* Request GPIOs. */
2726 for (i = 0; i < state->info->num_dv_ports; ++i) {
2727 state->hpd_gpio[i] =
Uwe Kleine-König269bd132015-03-02 04:00:44 -03002728 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
2729 GPIOD_OUT_LOW);
Laurent Pincharte9d50e92014-01-30 18:37:08 -03002730 if (IS_ERR(state->hpd_gpio[i]))
Uwe Kleine-König269bd132015-03-02 04:00:44 -03002731 return PTR_ERR(state->hpd_gpio[i]);
Laurent Pincharte9d50e92014-01-30 18:37:08 -03002732
Uwe Kleine-König269bd132015-03-02 04:00:44 -03002733 if (state->hpd_gpio[i])
2734 v4l_info(client, "Handling HPD %u GPIO\n", i);
Laurent Pincharte9d50e92014-01-30 18:37:08 -03002735 }
2736
Hans Verkuil591b72f2013-12-17 10:05:13 -03002737 state->timings = cea640x480;
Pablo Antonb44b2e02015-02-03 14:13:18 -03002738 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
Hans Verkuil54450f52012-07-18 05:45:16 -03002739
2740 sd = &state->sd;
Pablo Antonb44b2e02015-02-03 14:13:18 -03002741 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002742 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2743 id->name, i2c_adapter_id(client->adapter),
2744 client->addr);
Hans Verkuil54450f52012-07-18 05:45:16 -03002745 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
Hans Verkuil54450f52012-07-18 05:45:16 -03002746
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002747 /*
2748 * Verify that the chip is present. On ADV7604 the RD_INFO register only
2749 * identifies the revision, while on ADV7611 it identifies the model as
2750 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
2751 */
2752 if (state->info->type == ADV7604) {
2753 val = adv_smbus_read_byte_data_check(client, 0xfb, false);
2754 if (val != 0x68) {
2755 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2756 client->addr << 1);
2757 return -ENODEV;
2758 }
2759 } else {
2760 val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8)
2761 | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0);
2762 if (val != 0x2051) {
2763 v4l2_info(sd, "not an adv7611 on address 0x%x\n",
2764 client->addr << 1);
2765 return -ENODEV;
2766 }
Hans Verkuil54450f52012-07-18 05:45:16 -03002767 }
2768
2769 /* control handlers */
2770 hdl = &state->hdl;
Pablo Antonb44b2e02015-02-03 14:13:18 -03002771 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
Hans Verkuil54450f52012-07-18 05:45:16 -03002772
Pablo Antonb44b2e02015-02-03 14:13:18 -03002773 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
Hans Verkuil54450f52012-07-18 05:45:16 -03002774 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
Pablo Antonb44b2e02015-02-03 14:13:18 -03002775 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
Hans Verkuil54450f52012-07-18 05:45:16 -03002776 V4L2_CID_CONTRAST, 0, 255, 1, 128);
Pablo Antonb44b2e02015-02-03 14:13:18 -03002777 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
Hans Verkuil54450f52012-07-18 05:45:16 -03002778 V4L2_CID_SATURATION, 0, 255, 1, 128);
Pablo Antonb44b2e02015-02-03 14:13:18 -03002779 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
Hans Verkuil54450f52012-07-18 05:45:16 -03002780 V4L2_CID_HUE, 0, 128, 1, 0);
2781
2782 /* private controls */
2783 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002784 V4L2_CID_DV_RX_POWER_PRESENT, 0,
2785 (1 << state->info->num_dv_ports) - 1, 0, 0);
Hans Verkuil54450f52012-07-18 05:45:16 -03002786 state->rgb_quantization_range_ctrl =
Pablo Antonb44b2e02015-02-03 14:13:18 -03002787 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
Hans Verkuil54450f52012-07-18 05:45:16 -03002788 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2789 0, V4L2_DV_RGB_RANGE_AUTO);
Hans Verkuil54450f52012-07-18 05:45:16 -03002790
2791 /* custom controls */
Pablo Antonb44b2e02015-02-03 14:13:18 -03002792 if (adv76xx_has_afe(state))
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002793 state->analog_sampling_phase_ctrl =
2794 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
Hans Verkuil54450f52012-07-18 05:45:16 -03002795 state->free_run_color_manual_ctrl =
Pablo Antonb44b2e02015-02-03 14:13:18 -03002796 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
Hans Verkuil54450f52012-07-18 05:45:16 -03002797 state->free_run_color_ctrl =
Pablo Antonb44b2e02015-02-03 14:13:18 -03002798 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
Hans Verkuil54450f52012-07-18 05:45:16 -03002799
2800 sd->ctrl_handler = hdl;
2801 if (hdl->error) {
2802 err = hdl->error;
2803 goto err_hdl;
2804 }
Hans Verkuil8c0eadb2013-08-22 06:11:17 -03002805 state->detect_tx_5v_ctrl->is_private = true;
2806 state->rgb_quantization_range_ctrl->is_private = true;
Pablo Antonb44b2e02015-02-03 14:13:18 -03002807 if (adv76xx_has_afe(state))
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002808 state->analog_sampling_phase_ctrl->is_private = true;
Hans Verkuil8c0eadb2013-08-22 06:11:17 -03002809 state->free_run_color_manual_ctrl->is_private = true;
2810 state->free_run_color_ctrl->is_private = true;
2811
Pablo Antonb44b2e02015-02-03 14:13:18 -03002812 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
Hans Verkuil54450f52012-07-18 05:45:16 -03002813 err = -ENODEV;
2814 goto err_hdl;
2815 }
2816
Pablo Antonb44b2e02015-02-03 14:13:18 -03002817 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
Laurent Pinchart05cacb12014-01-30 16:32:21 -03002818 if (!(BIT(i) & state->info->page_mask))
2819 continue;
Hans Verkuil54450f52012-07-18 05:45:16 -03002820
Laurent Pinchart05cacb12014-01-30 16:32:21 -03002821 state->i2c_clients[i] =
Pablo Antonb44b2e02015-02-03 14:13:18 -03002822 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
Laurent Pinchart05cacb12014-01-30 16:32:21 -03002823 0xf2 + i);
2824 if (state->i2c_clients[i] == NULL) {
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002825 err = -ENOMEM;
Laurent Pinchart05cacb12014-01-30 16:32:21 -03002826 v4l2_err(sd, "failed to create i2c client %u\n", i);
Lars-Peter Clausend42010a2013-11-25 15:45:07 -03002827 goto err_i2c;
2828 }
2829 }
Laurent Pinchart05cacb12014-01-30 16:32:21 -03002830
Hans Verkuil54450f52012-07-18 05:45:16 -03002831 /* work queues */
2832 state->work_queues = create_singlethread_workqueue(client->name);
2833 if (!state->work_queues) {
2834 v4l2_err(sd, "Could not create work queue\n");
2835 err = -ENOMEM;
2836 goto err_i2c;
2837 }
2838
2839 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
Pablo Antonb44b2e02015-02-03 14:13:18 -03002840 adv76xx_delayed_work_enable_hotplug);
Hans Verkuil54450f52012-07-18 05:45:16 -03002841
Laurent Pinchartc784b1e2014-01-29 10:08:58 -03002842 state->source_pad = state->info->num_dv_ports
2843 + (state->info->has_afe ? 2 : 0);
2844 for (i = 0; i < state->source_pad; ++i)
2845 state->pads[i].flags = MEDIA_PAD_FL_SINK;
2846 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
2847
2848 err = media_entity_init(&sd->entity, state->source_pad + 1,
2849 state->pads, 0);
Hans Verkuil54450f52012-07-18 05:45:16 -03002850 if (err)
2851 goto err_work_queues;
2852
Pablo Antonb44b2e02015-02-03 14:13:18 -03002853 err = adv76xx_core_init(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -03002854 if (err)
2855 goto err_entity;
2856 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2857 client->addr << 1, client->adapter->name);
Lars-Peter Clausenbedc3932013-11-25 16:18:02 -03002858
2859 err = v4l2_async_register_subdev(sd);
2860 if (err)
2861 goto err_entity;
2862
Hans Verkuil54450f52012-07-18 05:45:16 -03002863 return 0;
2864
2865err_entity:
2866 media_entity_cleanup(&sd->entity);
2867err_work_queues:
2868 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2869 destroy_workqueue(state->work_queues);
2870err_i2c:
Pablo Antonb44b2e02015-02-03 14:13:18 -03002871 adv76xx_unregister_clients(state);
Hans Verkuil54450f52012-07-18 05:45:16 -03002872err_hdl:
2873 v4l2_ctrl_handler_free(hdl);
Hans Verkuil54450f52012-07-18 05:45:16 -03002874 return err;
2875}
2876
2877/* ----------------------------------------------------------------------- */
2878
Pablo Antonb44b2e02015-02-03 14:13:18 -03002879static int adv76xx_remove(struct i2c_client *client)
Hans Verkuil54450f52012-07-18 05:45:16 -03002880{
2881 struct v4l2_subdev *sd = i2c_get_clientdata(client);
Pablo Antonb44b2e02015-02-03 14:13:18 -03002882 struct adv76xx_state *state = to_state(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -03002883
2884 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2885 destroy_workqueue(state->work_queues);
Lars-Peter Clausenbedc3932013-11-25 16:18:02 -03002886 v4l2_async_unregister_subdev(sd);
Hans Verkuil54450f52012-07-18 05:45:16 -03002887 media_entity_cleanup(&sd->entity);
Pablo Antonb44b2e02015-02-03 14:13:18 -03002888 adv76xx_unregister_clients(to_state(sd));
Hans Verkuil54450f52012-07-18 05:45:16 -03002889 v4l2_ctrl_handler_free(sd->ctrl_handler);
Hans Verkuil54450f52012-07-18 05:45:16 -03002890 return 0;
2891}
2892
2893/* ----------------------------------------------------------------------- */
2894
Pablo Antonb44b2e02015-02-03 14:13:18 -03002895static struct i2c_driver adv76xx_driver = {
Hans Verkuil54450f52012-07-18 05:45:16 -03002896 .driver = {
2897 .owner = THIS_MODULE,
2898 .name = "adv7604",
Pablo Antonb44b2e02015-02-03 14:13:18 -03002899 .of_match_table = of_match_ptr(adv76xx_of_id),
Hans Verkuil54450f52012-07-18 05:45:16 -03002900 },
Pablo Antonb44b2e02015-02-03 14:13:18 -03002901 .probe = adv76xx_probe,
2902 .remove = adv76xx_remove,
2903 .id_table = adv76xx_i2c_id,
Hans Verkuil54450f52012-07-18 05:45:16 -03002904};
2905
Pablo Antonb44b2e02015-02-03 14:13:18 -03002906module_i2c_driver(adv76xx_driver);