andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 1 | /** @file
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| 2 |
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hhtian | 3d70643 | 2010-04-29 12:46:45 +0000 | [diff] [blame] | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 4 |
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hhtian | 3d70643 | 2010-04-29 12:46:45 +0000 | [diff] [blame] | 5 | This program and the accompanying materials
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 6 | are licensed and made available under the terms and conditions of the BSD License
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| 7 | which accompanies this distribution. The full text of the license may be found at
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| 8 | http://opensource.org/licenses/bsd-license.php
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| 9 |
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| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 12 |
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| 13 | **/
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| 14 |
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| 15 | #ifndef _MMCHS_H_
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| 16 | #define _MMCHS_H_
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| 17 |
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oliviermartin | 1e57a46 | 2013-01-25 11:28:06 +0000 | [diff] [blame] | 18 | #include <Uefi.h>
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andrewfish | 7f814ff | 2010-05-08 19:32:03 +0000 | [diff] [blame] | 19 |
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oliviermartin | 1e57a46 | 2013-01-25 11:28:06 +0000 | [diff] [blame] | 20 | #include <Library/BaseLib.h>
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| 21 | #include <Library/MemoryAllocationLib.h>
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| 22 | #include <Library/DebugLib.h>
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| 23 | #include <Library/IoLib.h>
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| 24 | #include <Library/PcdLib.h>
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| 25 | #include <Library/UefiBootServicesTableLib.h>
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| 26 | #include <Library/BaseMemoryLib.h>
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| 27 | #include <Library/OmapLib.h>
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| 28 | #include <Library/OmapDmaLib.h>
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| 29 | #include <Library/DmaLib.h>
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| 30 |
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 31 | #include <Protocol/EmbeddedExternalDevice.h>
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oliviermartin | 1e57a46 | 2013-01-25 11:28:06 +0000 | [diff] [blame] | 32 | #include <Protocol/BlockIo.h>
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| 33 | #include <Protocol/DevicePath.h>
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| 34 |
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 35 | #include <Omap3530/Omap3530.h>
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| 36 | #include <TPS65950.h>
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| 37 |
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oliviermartin | 1e57a46 | 2013-01-25 11:28:06 +0000 | [diff] [blame] | 38 | #define MAX_RETRY_COUNT (100*5)
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| 39 |
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andrewfish | 4326328 | 2010-04-03 00:34:19 +0000 | [diff] [blame] | 40 | #define HCS BIT30 //Host capacity support/1 = Supporting high capacity
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| 41 | #define CCS BIT30 //Card capacity status/1 = High capacity card
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 42 | typedef struct {
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Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 43 | UINT32 Reserved0: 7; // 0
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 44 | UINT32 V170_V195: 1; // 1.70V - 1.95V
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| 45 | UINT32 V200_V260: 7; // 2.00V - 2.60V
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| 46 | UINT32 V270_V360: 9; // 2.70V - 3.60V
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| 47 | UINT32 RESERVED_1: 5; // Reserved
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Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 48 | UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 49 | UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine
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| 50 | }OCR;
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| 51 |
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| 52 | typedef struct {
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| 53 | UINT32 NOT_USED; // 1 [0:0]
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| 54 | UINT32 CRC; // CRC7 checksum [7:1]
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| 55 | UINT32 MDT; // Manufacturing date [19:8]
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| 56 | UINT32 RESERVED_1; // Reserved [23:20]
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| 57 | UINT32 PSN; // Product serial number [55:24]
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| 58 | UINT8 PRV; // Product revision [63:56]
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| 59 | UINT8 PNM[5]; // Product name [64:103]
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| 60 | UINT16 OID; // OEM/Application ID [119:104]
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| 61 | UINT8 MID; // Manufacturer ID [127:120]
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| 62 | }CID;
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| 63 |
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| 64 | typedef struct {
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| 65 | UINT8 NOT_USED: 1; // Not used, always 1 [0:0]
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| 66 | UINT8 CRC: 7; // CRC [7:1]
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andrewfish | 8c6151f | 2010-04-30 19:43:11 +0000 | [diff] [blame] | 67 |
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 68 | UINT8 RESERVED_1: 2; // Reserved [9:8]
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| 69 | UINT8 FILE_FORMAT: 2; // File format [11:10]
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| 70 | UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
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| 71 | UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
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| 72 | UINT8 COPY: 1; // Copy flag (OTP) [14:14]
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| 73 | UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
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Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 74 |
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 75 | UINT16 RESERVED_2: 5; // Reserved [20:16]
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| 76 | UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
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| 77 | UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
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| 78 | UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
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| 79 | UINT16 RESERVED_3: 2; // Reserved [30:29]
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| 80 | UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
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Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 81 |
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 82 | UINT32 WP_GRP_SIZE: 7; // Write protect group size [38:32]
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| 83 | UINT32 SECTOR_SIZE: 7; // Erase sector size [45:39]
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| 84 | UINT32 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
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| 85 | UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]
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| 86 | UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]
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| 87 | UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
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| 88 | UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
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| 89 | UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
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andrewfish | 8c6151f | 2010-04-30 19:43:11 +0000 | [diff] [blame] | 90 | UINT32 C_SIZELow2: 2; // Device size [63:62]
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Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 91 |
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andrewfish | 8c6151f | 2010-04-30 19:43:11 +0000 | [diff] [blame] | 92 | UINT32 C_SIZEHigh10: 10;// Device size [73:64]
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 93 | UINT32 RESERVED_4: 2; // Reserved [75:74]
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| 94 | UINT32 DSR_IMP: 1; // DSR implemented [76:76]
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| 95 | UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
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| 96 | UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
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| 97 | UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
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| 98 | UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
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| 99 | UINT32 CCC: 12;// Card command classes [95:84]
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andrewfish | 8c6151f | 2010-04-30 19:43:11 +0000 | [diff] [blame] | 100 |
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 101 | UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
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| 102 | UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
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| 103 | UINT8 TAAC ; // Data read access-time 1 [119:112]
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Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 104 |
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 105 | UINT8 RESERVED_5: 6; // Reserved [125:120]
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| 106 | UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
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| 107 | }CSD;
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| 108 |
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| 109 | typedef struct {
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| 110 | UINT8 NOT_USED: 1; // Not used, always 1 [0:0]
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| 111 | UINT8 CRC: 7; // CRC [7:1]
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| 112 | UINT8 RESERVED_1: 2; // Reserved [9:8]
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| 113 | UINT8 FILE_FORMAT: 2; // File format [11:10]
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| 114 | UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
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| 115 | UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
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| 116 | UINT8 COPY: 1; // Copy flag (OTP) [14:14]
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| 117 | UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
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| 118 | UINT16 RESERVED_2: 5; // Reserved [20:16]
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| 119 | UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
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| 120 | UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
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| 121 | UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
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| 122 | UINT16 RESERVED_3: 2; // Reserved [30:29]
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| 123 | UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
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| 124 | UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32]
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| 125 | UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39]
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| 126 | UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
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| 127 | UINT16 RESERVED_4: 1; // Reserved [47:47]
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| 128 | UINT32 C_SIZELow16: 16;// Device size [69:48]
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| 129 | UINT32 C_SIZEHigh6: 6; // Device size [69:48]
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| 130 | UINT32 RESERVED_5: 6; // Reserved [75:70]
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| 131 | UINT32 DSR_IMP: 1; // DSR implemented [76:76]
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| 132 | UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
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| 133 | UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
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| 134 | UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
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| 135 | UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80]
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| 136 | UINT16 CCC: 12;// Card command classes [95:84]
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| 137 | UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
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| 138 | UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
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| 139 | UINT8 TAAC ; // Data read access-time 1 [119:112]
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| 140 | UINT8 RESERVED_6: 6; // 0 [125:120]
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| 141 | UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
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| 142 | }CSD_SDV2;
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| 143 |
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oliviermartin | 1e57a46 | 2013-01-25 11:28:06 +0000 | [diff] [blame] | 144 | typedef enum {
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| 145 | UNKNOWN_CARD,
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| 146 | MMC_CARD, //MMC card
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| 147 | SD_CARD, //SD 1.1 card
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| 148 | SD_CARD_2, //SD 2.0 or above standard card
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| 149 | SD_CARD_2_HIGH //SD 2.0 or above high capacity card
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 150 | } CARD_TYPE;
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| 151 |
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| 152 | typedef enum {
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| 153 | READ,
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| 154 | WRITE
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| 155 | } OPERATION_TYPE;
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| 156 |
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andrewfish | 8c6151f | 2010-04-30 19:43:11 +0000 | [diff] [blame] | 157 | typedef struct {
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 158 | UINT16 RCA;
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| 159 | UINTN BlockSize;
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| 160 | UINTN NumBlocks;
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| 161 | UINTN ClockFrequencySelect;
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| 162 | CARD_TYPE CardType;
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| 163 | OCR OCRData;
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| 164 | CID CIDData;
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| 165 | CSD CSDData;
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| 166 | } CARD_INFO;
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| 167 |
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oliviermartin | 1e57a46 | 2013-01-25 11:28:06 +0000 | [diff] [blame] | 168 | EFI_STATUS
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| 169 | DetectCard (
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| 170 | VOID
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andrewfish | 8c6151f | 2010-04-30 19:43:11 +0000 | [diff] [blame] | 171 | );
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| 172 |
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| 173 | extern EFI_BLOCK_IO_PROTOCOL gBlockIo;
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| 174 |
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andrewfish | a3f9864 | 2010-01-28 21:32:01 +0000 | [diff] [blame] | 175 | #endif
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