andrewfish | 7f814ff | 2010-05-08 19:32:03 +0000 | [diff] [blame] | 1 | /** @file
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| 2 | OMAP35xx DMA abstractions modeled on PCI IO protocol. EnableDma()/DisableDma()
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| 3 | are from OMAP35xx TRM.
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| 4 |
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| 5 | Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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| 6 |
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| 7 | This program and the accompanying materials
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| 8 | are licensed and made available under the terms and conditions of the BSD License
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| 9 | which accompanies this distribution. The full text of the license may be found at
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| 10 | http://opensource.org/licenses/bsd-license.php
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| 11 |
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| 12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 14 |
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| 15 | **/
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| 16 |
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| 17 | #include <Base.h>
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| 18 | #include <Library/DebugLib.h>
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| 19 | #include <Library/OmapDmaLib.h>
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| 20 | #include <Library/MemoryAllocationLib.h>
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| 21 | #include <Library/UefiBootServicesTableLib.h>
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| 22 | #include <Library/UncachedMemoryAllocationLib.h>
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| 23 | #include <Library/IoLib.h>
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| 24 | #include <Omap3530/Omap3530.h>
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| 25 |
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| 26 | #include <Protocol/Cpu.h>
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| 27 |
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| 28 | typedef struct {
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| 29 | EFI_PHYSICAL_ADDRESS HostAddress;
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| 30 | EFI_PHYSICAL_ADDRESS DeviceAddress;
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| 31 | UINTN NumberOfBytes;
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| 32 | DMA_MAP_OPERATION Operation;
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| 33 | } MAP_INFO_INSTANCE;
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| 34 |
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| 35 |
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| 36 |
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| 37 | EFI_CPU_ARCH_PROTOCOL *gCpu; |
| 38 |
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| 39 | /**
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| 40 | Configure OMAP DMA Channel
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| 41 |
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| 42 | @param Channel DMA Channel to configure
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| 43 | @param Dma4 Pointer to structure used to initialize DMA registers for the Channel
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| 44 |
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| 45 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
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| 46 | @retval EFI_INVALID_PARAMETER Channel is not valid
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| 47 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
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| 48 |
|
| 49 | **/ |
| 50 | EFI_STATUS |
| 51 | EFIAPI |
| 52 | EnableDmaChannel ( |
| 53 | IN UINTN Channel, |
| 54 | IN OMAP_DMA4 *DMA4 |
| 55 | ) |
| 56 | { |
| 57 | UINT32 RegVal; |
| 58 | |
| 59 | |
| 60 | if (Channel > DMA4_MAX_CHANNEL) { |
| 61 | return EFI_INVALID_PARAMETER; |
| 62 | } |
| 63 | |
| 64 | /* 1) Configure the transfer parameters in the logical DMA registers */
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| 65 | /*-------------------------------------------------------------------*/
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| 66 |
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| 67 | /* a) Set the data type CSDP[1:0], the Read/Write Port access type
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| 68 | CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19],
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| 69 | write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */
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| 70 |
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| 71 | // Read CSDP
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| 72 | RegVal = MmioRead32 (DMA4_CSDP (Channel));
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| 73 |
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| 74 | // Build reg
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| 75 | RegVal = ((RegVal & ~ 0x3) | DMA4->DataType );
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| 76 | RegVal = ((RegVal & ~(0x3 << 7)) | (DMA4->ReadPortAccessType << 7));
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| 77 | RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessType << 14));
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| 78 | RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21));
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| 79 | RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19));
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| 80 | RegVal = ((RegVal & ~(0x3 << 16)) | (DMA4->WriteMode << 16));
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| 81 | RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->SourcePacked << 6));
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| 82 | RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13));
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| 83 | // Write CSDP
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| 84 | MmioWrite32 (DMA4_CSDP (Channel), RegVal);
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| 85 |
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| 86 | /* b) Set the number of element per frame CEN[23:0]*/
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| 87 | MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame);
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| 88 |
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| 89 | /* c) Set the number of frame per block CFN[15:0]*/
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| 90 | MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock);
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| 91 |
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| 92 | /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/
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| 93 | MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress);
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| 94 | MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress);
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| 95 |
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| 96 | /* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14],
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| 97 | read/write priority CCR[6]/CCR[26]
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| 98 | I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to
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| 99 | LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber
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| 100 | */
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| 101 |
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| 102 | // Read CCR
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| 103 | RegVal = MmioRead32 (DMA4_CCR (Channel));
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| 104 |
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| 105 | // Build reg
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| 106 | RegVal = ((RegVal & ~0x1f) | DMA4->ReadRequestNumber);
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| 107 | RegVal = ((RegVal & ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19);
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| 108 | RegVal = ((RegVal & ~(0x3 << 12)) | (DMA4->ReadPortAccessMode << 12));
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| 109 | RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessMode << 14));
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| 110 | RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->ReadPriority << 6));
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| 111 | RegVal = ((RegVal & ~(0x1 << 26)) | (DMA4->WritePriority << 26));
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| 112 |
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| 113 | // Write CCR
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| 114 | MmioWrite32 (DMA4_CCR (Channel), RegVal);
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| 115 |
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| 116 | /* f)- Set the source element index CSEI[15:0]*/
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| 117 | MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex);
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| 118 |
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| 119 | /* - Set the source frame index CSFI[15:0]*/
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| 120 | MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex);
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| 121 |
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| 122 |
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| 123 | /* - Set the destination element index CDEI[15:0]*/
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| 124 | MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex);
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| 125 |
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| 126 | /* - Set the destination frame index CDFI[31:0]*/
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| 127 | MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);
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andrewfish | 9f6b977 | 2010-05-11 00:06:47 +0000 | [diff] [blame^] | 128 |
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| 129 | MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);
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| 130 |
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| 131 | // Enable all the status bits since we are polling
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| 132 | MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL);
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| 133 | MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);
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| 134 |
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andrewfish | 7f814ff | 2010-05-08 19:32:03 +0000 | [diff] [blame] | 135 | /* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */
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| 136 | /*--------------------------------------------------------------*/
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| 137 | //write enable bit
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andrewfish | 9f6b977 | 2010-05-11 00:06:47 +0000 | [diff] [blame^] | 138 | MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer |
andrewfish | 7f814ff | 2010-05-08 19:32:03 +0000 | [diff] [blame] | 139 | |
| 140 | return EFI_SUCCESS; |
| 141 | } |
| 142 | |
| 143 | /**
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| 144 | Turn of DMA channel configured by EnableDma().
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| 145 |
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| 146 | @param Channel DMA Channel to configure
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andrewfish | 9f6b977 | 2010-05-11 00:06:47 +0000 | [diff] [blame^] | 147 | @param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS
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| 148 | @param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR
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andrewfish | 7f814ff | 2010-05-08 19:32:03 +0000 | [diff] [blame] | 149 |
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| 150 | @retval EFI_SUCCESS DMA hardware disabled
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| 151 | @retval EFI_INVALID_PARAMETER Channel is not valid
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| 152 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
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| 153 |
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| 154 | **/ |
| 155 | EFI_STATUS |
| 156 | EFIAPI |
| 157 | DisableDmaChannel ( |
andrewfish | 9f6b977 | 2010-05-11 00:06:47 +0000 | [diff] [blame^] | 158 | IN UINTN Channel, |
| 159 | IN UINT32 SuccessMask, |
| 160 | IN UINT32 ErrorMask |
andrewfish | 7f814ff | 2010-05-08 19:32:03 +0000 | [diff] [blame] | 161 | ) |
| 162 | { |
andrewfish | 9f6b977 | 2010-05-11 00:06:47 +0000 | [diff] [blame^] | 163 | EFI_STATUS Status = EFI_SUCCESS; |
| 164 | UINT32 Reg; |
| 165 | |
| 166 | |
andrewfish | 7f814ff | 2010-05-08 19:32:03 +0000 | [diff] [blame] | 167 | if (Channel > DMA4_MAX_CHANNEL) { |
| 168 | return EFI_INVALID_PARAMETER; |
| 169 | } |
| 170 | |
andrewfish | 9f6b977 | 2010-05-11 00:06:47 +0000 | [diff] [blame^] | 171 | do { |
| 172 | Reg = MmioRead32 (DMA4_CSR(Channel)); |
| 173 | if ((Reg & ErrorMask) != 0) { |
| 174 | Status = EFI_DEVICE_ERROR; |
| 175 | DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg)); |
| 176 | break; |
| 177 | } |
| 178 | } while ((Reg & SuccessMask) != SuccessMask); |
| 179 | |
| 180 | |
| 181 | // Disable all status bits and clear them |
| 182 | MmioWrite32 (DMA4_CICR (Channel), 0);
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| 183 | MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET); |
| 184 | |
andrewfish | 7f814ff | 2010-05-08 19:32:03 +0000 | [diff] [blame] | 185 | MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE)); |
andrewfish | 9f6b977 | 2010-05-11 00:06:47 +0000 | [diff] [blame^] | 186 | return Status; |
andrewfish | 7f814ff | 2010-05-08 19:32:03 +0000 | [diff] [blame] | 187 | } |
| 188 | |
andrewfish | 9f6b977 | 2010-05-11 00:06:47 +0000 | [diff] [blame^] | 189 | |
| 190 | |
andrewfish | 7f814ff | 2010-05-08 19:32:03 +0000 | [diff] [blame] | 191 | /**
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| 192 | Provides the DMA controller-specific addresses needed to access system memory.
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| 193 |
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| 194 | Operation is relative to the DMA bus master.
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| 195 |
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| 196 | @param Operation Indicates if the bus master is going to read or write to system memory.
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| 197 | @param HostAddress The system memory address to map to the DMA controller.
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| 198 | @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
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| 199 | that were mapped.
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| 200 | @param DeviceAddress The resulting map address for the bus master controller to use to
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| 201 | access the hosts HostAddress.
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| 202 | @param Mapping A resulting value to pass to Unmap().
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| 203 |
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| 204 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
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| 205 | @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
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| 206 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
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| 207 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
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| 208 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
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| 209 |
|
| 210 | **/ |
| 211 | EFI_STATUS |
| 212 | EFIAPI |
| 213 | DmaMap ( |
| 214 | IN DMA_MAP_OPERATION Operation, |
| 215 | IN VOID *HostAddress,
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| 216 | IN OUT UINTN *NumberOfBytes,
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| 217 | OUT PHYSICAL_ADDRESS *DeviceAddress,
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| 218 | OUT VOID **Mapping
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| 219 | ) |
| 220 | { |
| 221 | MAP_INFO_INSTANCE *Map; |
| 222 | |
| 223 | if ( HostAddress == NULL || NumberOfBytes == NULL || |
| 224 | DeviceAddress == NULL || Mapping == NULL ) { |
| 225 | return EFI_INVALID_PARAMETER; |
| 226 | } |
| 227 | |
| 228 | |
| 229 | if (Operation >= MapOperationMaximum) { |
| 230 | return EFI_INVALID_PARAMETER; |
| 231 | } |
| 232 | |
| 233 | *DeviceAddress = ConvertToPhysicalAddress (HostAddress); |
| 234 | |
| 235 | // Remember range so we can flush on the other side |
| 236 | Map = AllocatePool (sizeof (MAP_INFO_INSTANCE)); |
| 237 | if (Map == NULL) { |
| 238 | return EFI_OUT_OF_RESOURCES; |
| 239 | } |
| 240 | |
| 241 | *Mapping = Map; |
| 242 | |
| 243 | Map->HostAddress = (UINTN)HostAddress; |
| 244 | Map->DeviceAddress = *DeviceAddress; |
| 245 | Map->NumberOfBytes = *NumberOfBytes; |
| 246 | Map->Operation = Operation; |
| 247 | |
| 248 | // EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate |
| 249 | gCpu->FlushDataCache (gCpu, (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate); |
| 250 | |
| 251 | return EFI_SUCCESS; |
| 252 | } |
| 253 | |
| 254 | |
| 255 | /**
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| 256 | Completes the DmaMapBusMasterRead(), DmaMapBusMasterWrite(), or DmaMapBusMasterCommonBuffer()
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| 257 | operation and releases any corresponding resources.
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| 258 |
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| 259 | @param Mapping The mapping value returned from DmaMap*().
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| 260 |
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| 261 | @retval EFI_SUCCESS The range was unmapped.
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| 262 | @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
|
| 263 |
|
| 264 | **/ |
| 265 | EFI_STATUS |
| 266 | EFIAPI |
| 267 | DmaUnmap ( |
| 268 | IN VOID *Mapping
|
| 269 | ) |
| 270 | { |
| 271 | MAP_INFO_INSTANCE *Map; |
| 272 | |
| 273 | if (Mapping == NULL) { |
| 274 | ASSERT (FALSE); |
| 275 | return EFI_INVALID_PARAMETER; |
| 276 | } |
| 277 | |
| 278 | Map = (MAP_INFO_INSTANCE *)Mapping; |
| 279 | if (Map->Operation == MapOperationBusMasterWrite) { |
| 280 | // |
| 281 | // Make sure we read buffer from uncached memory and not the cache |
| 282 | // |
| 283 | gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate); |
| 284 | } |
| 285 | |
| 286 | FreePool (Map); |
| 287 | |
| 288 | return EFI_SUCCESS; |
| 289 | } |
| 290 | |
| 291 | /**
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| 292 | Allocates pages that are suitable for an DmaMap() of type MapOperationBusMasterCommonBuffer.
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| 293 | mapping.
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| 294 |
|
| 295 | @param MemoryType The type of memory to allocate, EfiBootServicesData or
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| 296 | EfiRuntimeServicesData.
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| 297 | @param Pages The number of pages to allocate.
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| 298 | @param HostAddress A pointer to store the base system memory address of the
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| 299 | allocated range.
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| 300 |
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| 301 | @retval EFI_SUCCESS The requested memory pages were allocated.
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| 302 | @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
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| 303 | MEMORY_WRITE_COMBINE and MEMORY_CACHED.
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| 304 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
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| 305 | @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
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| 306 |
|
| 307 | **/EFI_STATUS |
| 308 | EFIAPI |
| 309 | DmaAllocateBuffer ( |
| 310 | IN EFI_MEMORY_TYPE MemoryType, |
| 311 | IN UINTN Pages,
|
| 312 | OUT VOID **HostAddress
|
| 313 | )
|
| 314 | { |
| 315 | if (HostAddress == NULL) { |
| 316 | return EFI_INVALID_PARAMETER; |
| 317 | } |
| 318 | |
| 319 | // |
| 320 | // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData |
| 321 | // |
| 322 | // We used uncached memory to keep coherency |
| 323 | // |
| 324 | if (MemoryType == EfiBootServicesData) { |
| 325 | *HostAddress = UncachedAllocatePages (Pages); |
| 326 | } else if (MemoryType != EfiRuntimeServicesData) { |
| 327 | *HostAddress = UncachedAllocateRuntimePages (Pages); |
| 328 | } else { |
| 329 | return EFI_INVALID_PARAMETER; |
| 330 | } |
| 331 | |
| 332 | return EFI_SUCCESS; |
| 333 | } |
| 334 | |
| 335 | |
| 336 | /**
|
| 337 | Frees memory that was allocated with DmaAllocateBuffer().
|
| 338 |
|
| 339 | @param Pages The number of pages to free.
|
| 340 | @param HostAddress The base system memory address of the allocated range.
|
| 341 |
|
| 342 | @retval EFI_SUCCESS The requested memory pages were freed.
|
| 343 | @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
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| 344 | was not allocated with DmaAllocateBuffer().
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| 345 |
|
| 346 | **/
|
| 347 | EFI_STATUS |
| 348 | EFIAPI |
| 349 | DmaFreeBuffer ( |
| 350 | IN UINTN Pages,
|
| 351 | IN VOID *HostAddress
|
| 352 | )
|
| 353 | { |
| 354 | if (HostAddress == NULL) { |
| 355 | return EFI_INVALID_PARAMETER; |
| 356 | } |
| 357 | |
| 358 | UncachedFreePages (HostAddress, Pages); |
| 359 | return EFI_SUCCESS; |
| 360 | } |
| 361 | |
| 362 | |
| 363 | EFI_STATUS |
| 364 | EFIAPI |
| 365 | OmapDmaLibConstructor ( |
| 366 | IN EFI_HANDLE ImageHandle, |
| 367 | IN EFI_SYSTEM_TABLE *SystemTable |
| 368 | ) |
| 369 | { |
| 370 | EFI_STATUS Status; |
| 371 | |
| 372 | // Get the Cpu protocol for later use |
| 373 | Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu); |
| 374 | ASSERT_EFI_ERROR(Status); |
| 375 | |
| 376 | return EFI_SUCCESS; |
| 377 | } |
| 378 | |