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Aart Bikf8f5a162017-02-06 15:35:29 -08001/*
2 * Copyright (C) 2017 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_OPTIMIZING_NODES_VECTOR_H_
18#define ART_COMPILER_OPTIMIZING_NODES_VECTOR_H_
19
20// This #include should never be used by compilation, because this header file (nodes_vector.h)
21// is included in the header file nodes.h itself. However it gives editing tools better context.
22#include "nodes.h"
23
24namespace art {
25
26// Memory alignment, represented as an offset relative to a base, where 0 <= offset < base,
27// and base is a power of two. For example, the value Alignment(16, 0) means memory is
28// perfectly aligned at a 16-byte boundary, whereas the value Alignment(16, 4) means
29// memory is always exactly 4 bytes above such a boundary.
30class Alignment {
31 public:
32 Alignment(size_t base, size_t offset) : base_(base), offset_(offset) {
33 DCHECK_LT(offset, base);
34 DCHECK(IsPowerOfTwo(base));
35 }
36
Aart Bik46b6dbc2017-10-03 11:37:37 -070037 // Returns true if memory is at least aligned at the given boundary.
Aart Bikf8f5a162017-02-06 15:35:29 -080038 // Assumes requested base is power of two.
39 bool IsAlignedAt(size_t base) const {
40 DCHECK_NE(0u, base);
41 DCHECK(IsPowerOfTwo(base));
42 return ((offset_ | base_) & (base - 1u)) == 0;
43 }
44
Aart Bik46b6dbc2017-10-03 11:37:37 -070045 size_t Base() const { return base_; }
46
47 size_t Offset() const { return offset_; }
48
Aart Bikf8f5a162017-02-06 15:35:29 -080049 std::string ToString() const {
50 return "ALIGN(" + std::to_string(base_) + "," + std::to_string(offset_) + ")";
51 }
52
Aart Bikb79f4ac2017-07-10 10:10:37 -070053 bool operator==(const Alignment& other) const {
54 return base_ == other.base_ && offset_ == other.offset_;
55 }
56
Aart Bikf8f5a162017-02-06 15:35:29 -080057 private:
58 size_t base_;
59 size_t offset_;
60};
61
62//
63// Definitions of abstract vector operations in HIR.
64//
65
66// Abstraction of a vector operation, i.e., an operation that performs
67// GetVectorLength() x GetPackedType() operations simultaneously.
68class HVecOperation : public HVariableInputSizeInstruction {
69 public:
Aart Bik0148de42017-09-05 09:25:01 -070070 // A SIMD operation looks like a FPU location.
71 // TODO: we could introduce SIMD types in HIR.
Vladimir Marko0ebe0d82017-09-21 22:50:39 +010072 static constexpr DataType::Type kSIMDType = DataType::Type::kFloat64;
Aart Bik0148de42017-09-05 09:25:01 -070073
Vladimir Markoe764d2e2017-10-05 14:35:55 +010074 HVecOperation(ArenaAllocator* allocator,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +010075 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -080076 SideEffects side_effects,
77 size_t number_of_inputs,
78 size_t vector_length,
79 uint32_t dex_pc)
80 : HVariableInputSizeInstruction(side_effects,
81 dex_pc,
Vladimir Markoe764d2e2017-10-05 14:35:55 +010082 allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -080083 number_of_inputs,
84 kArenaAllocVectorNode),
85 vector_length_(vector_length) {
86 SetPackedField<TypeField>(packed_type);
87 DCHECK_LT(1u, vector_length);
88 }
89
90 // Returns the number of elements packed in a vector.
91 size_t GetVectorLength() const {
92 return vector_length_;
93 }
94
95 // Returns the number of bytes in a full vector.
96 size_t GetVectorNumberOfBytes() const {
Vladimir Marko0ebe0d82017-09-21 22:50:39 +010097 return vector_length_ * DataType::Size(GetPackedType());
Aart Bikf8f5a162017-02-06 15:35:29 -080098 }
99
Aart Bik0148de42017-09-05 09:25:01 -0700100 // Returns the type of the vector operation.
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100101 DataType::Type GetType() const OVERRIDE {
Aart Bik0148de42017-09-05 09:25:01 -0700102 return kSIMDType;
Aart Bikf8f5a162017-02-06 15:35:29 -0800103 }
104
105 // Returns the true component type packed in a vector.
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100106 DataType::Type GetPackedType() const {
Aart Bikf8f5a162017-02-06 15:35:29 -0800107 return GetPackedField<TypeField>();
108 }
109
Aart Bikb79f4ac2017-07-10 10:10:37 -0700110 // Assumes vector nodes cannot be moved by default. Each concrete implementation
111 // that can be moved should override this method and return true.
112 bool CanBeMoved() const OVERRIDE { return false; }
113
114 // Tests if all data of a vector node (vector length and packed type) is equal.
115 // Each concrete implementation that adds more fields should test equality of
116 // those fields in its own method *and* call all super methods.
117 bool InstructionDataEquals(const HInstruction* other) const OVERRIDE {
118 DCHECK(other->IsVecOperation());
119 const HVecOperation* o = other->AsVecOperation();
120 return GetVectorLength() == o->GetVectorLength() && GetPackedType() == o->GetPackedType();
121 }
122
Aart Bik46b6dbc2017-10-03 11:37:37 -0700123 // Maps an integral type to the same-size signed type and leaves other types alone.
124 // Can be used to test relaxed type consistency in which packed same-size integral
125 // types can co-exist, but other type mixes are an error.
126 static DataType::Type ToSignedType(DataType::Type type) {
127 switch (type) {
128 case DataType::Type::kBool: // 1-byte storage unit
129 case DataType::Type::kUint8:
130 return DataType::Type::kInt8;
131 case DataType::Type::kUint16:
132 return DataType::Type::kInt16;
133 default:
134 DCHECK(type != DataType::Type::kVoid && type != DataType::Type::kReference) << type;
135 return type;
136 }
137 }
138
Aart Bik4d1a9d42017-10-19 14:40:55 -0700139 // Maps an integral type to the same-size unsigned type and leaves other types alone.
140 static DataType::Type ToUnsignedType(DataType::Type type) {
141 switch (type) {
142 case DataType::Type::kBool: // 1-byte storage unit
143 case DataType::Type::kInt8:
144 return DataType::Type::kUint8;
145 case DataType::Type::kInt16:
146 return DataType::Type::kUint16;
147 default:
148 DCHECK(type != DataType::Type::kVoid && type != DataType::Type::kReference) << type;
149 return type;
150 }
151 }
152
Aart Bik2dd7b672017-12-07 11:11:22 -0800153 // Helper method to determine if an instruction returns a SIMD value.
154 // TODO: This method is needed until we introduce SIMD as proper type.
155 static bool ReturnsSIMDValue(HInstruction* instruction) {
156 if (instruction->IsVecOperation()) {
157 return !instruction->IsVecExtractScalar(); // only scalar returning vec op
158 } else if (instruction->IsPhi()) {
159 return
160 instruction->GetType() == kSIMDType &&
161 instruction->InputAt(1)->IsVecOperation(); // vectorizer does not go deeper
162 }
163 return false;
164 }
165
Aart Bikf8f5a162017-02-06 15:35:29 -0800166 DECLARE_ABSTRACT_INSTRUCTION(VecOperation);
167
Aart Bikdb14fcf2017-04-25 15:53:58 -0700168 protected:
Aart Bikf8f5a162017-02-06 15:35:29 -0800169 // Additional packed bits.
170 static constexpr size_t kFieldType = HInstruction::kNumberOfGenericPackedBits;
171 static constexpr size_t kFieldTypeSize =
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100172 MinimumBitsToStore(static_cast<size_t>(DataType::Type::kLast));
Aart Bikf8f5a162017-02-06 15:35:29 -0800173 static constexpr size_t kNumberOfVectorOpPackedBits = kFieldType + kFieldTypeSize;
174 static_assert(kNumberOfVectorOpPackedBits <= kMaxNumberOfPackedBits, "Too many packed fields.");
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100175 using TypeField = BitField<DataType::Type, kFieldType, kFieldTypeSize>;
Aart Bikf8f5a162017-02-06 15:35:29 -0800176
Artem Serovcced8ba2017-07-19 18:18:09 +0100177 DEFAULT_COPY_CONSTRUCTOR(VecOperation);
178
Aart Bikdb14fcf2017-04-25 15:53:58 -0700179 private:
Aart Bikf8f5a162017-02-06 15:35:29 -0800180 const size_t vector_length_;
Aart Bikf8f5a162017-02-06 15:35:29 -0800181};
182
183// Abstraction of a unary vector operation.
184class HVecUnaryOperation : public HVecOperation {
185 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100186 HVecUnaryOperation(ArenaAllocator* allocator,
Aart Bik8de59162017-04-21 09:42:01 -0700187 HInstruction* input,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100188 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800189 size_t vector_length,
190 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100191 : HVecOperation(allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800192 packed_type,
193 SideEffects::None(),
Aart Bik8de59162017-04-21 09:42:01 -0700194 /* number_of_inputs */ 1,
Aart Bikf8f5a162017-02-06 15:35:29 -0800195 vector_length,
Aart Bik8de59162017-04-21 09:42:01 -0700196 dex_pc) {
197 SetRawInputAt(0, input);
198 }
199
200 HInstruction* GetInput() const { return InputAt(0); }
201
Aart Bikf8f5a162017-02-06 15:35:29 -0800202 DECLARE_ABSTRACT_INSTRUCTION(VecUnaryOperation);
Aart Bik8de59162017-04-21 09:42:01 -0700203
Artem Serovcced8ba2017-07-19 18:18:09 +0100204 protected:
205 DEFAULT_COPY_CONSTRUCTOR(VecUnaryOperation);
Aart Bikf8f5a162017-02-06 15:35:29 -0800206};
207
208// Abstraction of a binary vector operation.
209class HVecBinaryOperation : public HVecOperation {
210 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100211 HVecBinaryOperation(ArenaAllocator* allocator,
Aart Bik8de59162017-04-21 09:42:01 -0700212 HInstruction* left,
213 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100214 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800215 size_t vector_length,
216 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100217 : HVecOperation(allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800218 packed_type,
219 SideEffects::None(),
Aart Bik8de59162017-04-21 09:42:01 -0700220 /* number_of_inputs */ 2,
Aart Bikf8f5a162017-02-06 15:35:29 -0800221 vector_length,
Aart Bik8de59162017-04-21 09:42:01 -0700222 dex_pc) {
223 SetRawInputAt(0, left);
224 SetRawInputAt(1, right);
225 }
Artem Serovf34dd202017-04-10 17:41:46 +0100226
227 HInstruction* GetLeft() const { return InputAt(0); }
228 HInstruction* GetRight() const { return InputAt(1); }
229
Aart Bikf8f5a162017-02-06 15:35:29 -0800230 DECLARE_ABSTRACT_INSTRUCTION(VecBinaryOperation);
Aart Bik8de59162017-04-21 09:42:01 -0700231
Artem Serovcced8ba2017-07-19 18:18:09 +0100232 protected:
233 DEFAULT_COPY_CONSTRUCTOR(VecBinaryOperation);
Aart Bikf8f5a162017-02-06 15:35:29 -0800234};
235
236// Abstraction of a vector operation that references memory, with an alignment.
Aart Bik46b6dbc2017-10-03 11:37:37 -0700237// The Android runtime guarantees elements have at least natural alignment.
Aart Bikf8f5a162017-02-06 15:35:29 -0800238class HVecMemoryOperation : public HVecOperation {
239 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100240 HVecMemoryOperation(ArenaAllocator* allocator,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100241 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800242 SideEffects side_effects,
243 size_t number_of_inputs,
244 size_t vector_length,
245 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100246 : HVecOperation(allocator,
247 packed_type,
248 side_effects,
249 number_of_inputs,
250 vector_length,
251 dex_pc),
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100252 alignment_(DataType::Size(packed_type), 0) {
Artem Serove1811ed2017-04-27 16:50:47 +0100253 DCHECK_GE(number_of_inputs, 2u);
254 }
Aart Bikf8f5a162017-02-06 15:35:29 -0800255
256 void SetAlignment(Alignment alignment) { alignment_ = alignment; }
257
258 Alignment GetAlignment() const { return alignment_; }
259
Artem Serove1811ed2017-04-27 16:50:47 +0100260 HInstruction* GetArray() const { return InputAt(0); }
261 HInstruction* GetIndex() const { return InputAt(1); }
262
Aart Bikb79f4ac2017-07-10 10:10:37 -0700263 bool InstructionDataEquals(const HInstruction* other) const OVERRIDE {
264 DCHECK(other->IsVecMemoryOperation());
265 const HVecMemoryOperation* o = other->AsVecMemoryOperation();
266 return HVecOperation::InstructionDataEquals(o) && GetAlignment() == o->GetAlignment();
267 }
268
Aart Bikf8f5a162017-02-06 15:35:29 -0800269 DECLARE_ABSTRACT_INSTRUCTION(VecMemoryOperation);
270
Artem Serovcced8ba2017-07-19 18:18:09 +0100271 protected:
272 DEFAULT_COPY_CONSTRUCTOR(VecMemoryOperation);
273
Aart Bikf8f5a162017-02-06 15:35:29 -0800274 private:
275 Alignment alignment_;
Aart Bikf8f5a162017-02-06 15:35:29 -0800276};
277
Aart Bik0148de42017-09-05 09:25:01 -0700278// Packed type consistency checker ("same vector length" integral types may mix freely).
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100279inline static bool HasConsistentPackedTypes(HInstruction* input, DataType::Type type) {
Aart Bik0148de42017-09-05 09:25:01 -0700280 if (input->IsPhi()) {
281 return input->GetType() == HVecOperation::kSIMDType; // carries SIMD
282 }
Aart Bikd58bc322017-05-01 14:49:18 -0700283 DCHECK(input->IsVecOperation());
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100284 DataType::Type input_type = input->AsVecOperation()->GetPackedType();
Aart Bik4d1a9d42017-10-19 14:40:55 -0700285 DCHECK_EQ(HVecOperation::ToUnsignedType(input_type) == HVecOperation::ToUnsignedType(type),
286 HVecOperation::ToSignedType(input_type) == HVecOperation::ToSignedType(type));
Aart Bik46b6dbc2017-10-03 11:37:37 -0700287 return HVecOperation::ToSignedType(input_type) == HVecOperation::ToSignedType(type);
Aart Bikd58bc322017-05-01 14:49:18 -0700288}
289
Aart Bikf8f5a162017-02-06 15:35:29 -0800290//
Aart Bik8de59162017-04-21 09:42:01 -0700291// Definitions of concrete unary vector operations in HIR.
Aart Bikf8f5a162017-02-06 15:35:29 -0800292//
293
294// Replicates the given scalar into a vector,
295// viz. replicate(x) = [ x, .. , x ].
296class HVecReplicateScalar FINAL : public HVecUnaryOperation {
297 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100298 HVecReplicateScalar(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800299 HInstruction* scalar,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100300 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800301 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700302 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100303 : HVecUnaryOperation(allocator, scalar, packed_type, vector_length, dex_pc) {
Aart Bik8de59162017-04-21 09:42:01 -0700304 DCHECK(!scalar->IsVecOperation());
Aart Bikf8f5a162017-02-06 15:35:29 -0800305 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700306
307 // A replicate needs to stay in place, since SIMD registers are not
308 // kept alive across vector loop boundaries (yet).
309 bool CanBeMoved() const OVERRIDE { return false; }
310
Aart Bikf8f5a162017-02-06 15:35:29 -0800311 DECLARE_INSTRUCTION(VecReplicateScalar);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700312
Artem Serovcced8ba2017-07-19 18:18:09 +0100313 protected:
314 DEFAULT_COPY_CONSTRUCTOR(VecReplicateScalar);
Aart Bikf8f5a162017-02-06 15:35:29 -0800315};
316
Aart Bik0148de42017-09-05 09:25:01 -0700317// Extracts a particular scalar from the given vector,
318// viz. extract[ x1, .. , xn ] = x_i.
319//
320// TODO: for now only i == 1 case supported.
321class HVecExtractScalar FINAL : public HVecUnaryOperation {
322 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100323 HVecExtractScalar(ArenaAllocator* allocator,
Aart Bik0148de42017-09-05 09:25:01 -0700324 HInstruction* input,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100325 DataType::Type packed_type,
Aart Bik0148de42017-09-05 09:25:01 -0700326 size_t vector_length,
327 size_t index,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700328 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100329 : HVecUnaryOperation(allocator, input, packed_type, vector_length, dex_pc) {
Aart Bikd58bc322017-05-01 14:49:18 -0700330 DCHECK(HasConsistentPackedTypes(input, packed_type));
Aart Bik0148de42017-09-05 09:25:01 -0700331 DCHECK_LT(index, vector_length);
332 DCHECK_EQ(index, 0u);
333 }
334
335 // Yields a single component in the vector.
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100336 DataType::Type GetType() const OVERRIDE {
Aart Bik0148de42017-09-05 09:25:01 -0700337 return GetPackedType();
338 }
339
340 // An extract needs to stay in place, since SIMD registers are not
341 // kept alive across vector loop boundaries (yet).
342 bool CanBeMoved() const OVERRIDE { return false; }
343
344 DECLARE_INSTRUCTION(VecExtractScalar);
345
Artem Serovcced8ba2017-07-19 18:18:09 +0100346 protected:
347 DEFAULT_COPY_CONSTRUCTOR(VecExtractScalar);
Aart Bik0148de42017-09-05 09:25:01 -0700348};
349
350// Reduces the given vector into the first element as sum/min/max,
351// viz. sum-reduce[ x1, .. , xn ] = [ y, ---- ], where y = sum xi
352// and the "-" denotes "don't care" (implementation dependent).
353class HVecReduce FINAL : public HVecUnaryOperation {
354 public:
355 enum ReductionKind {
356 kSum = 1,
357 kMin = 2,
358 kMax = 3
359 };
360
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100361 HVecReduce(ArenaAllocator* allocator,
Aart Bik0148de42017-09-05 09:25:01 -0700362 HInstruction* input,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100363 DataType::Type packed_type,
Aart Bik0148de42017-09-05 09:25:01 -0700364 size_t vector_length,
365 ReductionKind kind,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700366 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100367 : HVecUnaryOperation(allocator, input, packed_type, vector_length, dex_pc),
Aart Bik0148de42017-09-05 09:25:01 -0700368 kind_(kind) {
369 DCHECK(HasConsistentPackedTypes(input, packed_type));
Aart Bikcfa59b42017-08-31 09:08:13 -0700370 }
371
Aart Bik0148de42017-09-05 09:25:01 -0700372 ReductionKind GetKind() const { return kind_; }
Aart Bikf8f5a162017-02-06 15:35:29 -0800373
Aart Bikb79f4ac2017-07-10 10:10:37 -0700374 bool CanBeMoved() const OVERRIDE { return true; }
375
Aart Bik0148de42017-09-05 09:25:01 -0700376 bool InstructionDataEquals(const HInstruction* other) const OVERRIDE {
377 DCHECK(other->IsVecReduce());
378 const HVecReduce* o = other->AsVecReduce();
379 return HVecOperation::InstructionDataEquals(o) && GetKind() == o->GetKind();
380 }
381
382 DECLARE_INSTRUCTION(VecReduce);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700383
Artem Serovcced8ba2017-07-19 18:18:09 +0100384 protected:
385 DEFAULT_COPY_CONSTRUCTOR(VecReduce);
386
Aart Bikf8f5a162017-02-06 15:35:29 -0800387 private:
Aart Bik0148de42017-09-05 09:25:01 -0700388 const ReductionKind kind_;
Aart Bikf8f5a162017-02-06 15:35:29 -0800389};
390
391// Converts every component in the vector,
392// viz. cnv[ x1, .. , xn ] = [ cnv(x1), .. , cnv(xn) ].
393class HVecCnv FINAL : public HVecUnaryOperation {
394 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100395 HVecCnv(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800396 HInstruction* input,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100397 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800398 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700399 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100400 : HVecUnaryOperation(allocator, input, packed_type, vector_length, dex_pc) {
Aart Bikf8f5a162017-02-06 15:35:29 -0800401 DCHECK(input->IsVecOperation());
Aart Bikd58bc322017-05-01 14:49:18 -0700402 DCHECK_NE(GetInputType(), GetResultType()); // actual convert
Aart Bikf8f5a162017-02-06 15:35:29 -0800403 }
404
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100405 DataType::Type GetInputType() const { return InputAt(0)->AsVecOperation()->GetPackedType(); }
406 DataType::Type GetResultType() const { return GetPackedType(); }
Aart Bikf8f5a162017-02-06 15:35:29 -0800407
Aart Bikb79f4ac2017-07-10 10:10:37 -0700408 bool CanBeMoved() const OVERRIDE { return true; }
409
Aart Bikf8f5a162017-02-06 15:35:29 -0800410 DECLARE_INSTRUCTION(VecCnv);
411
Artem Serovcced8ba2017-07-19 18:18:09 +0100412 protected:
413 DEFAULT_COPY_CONSTRUCTOR(VecCnv);
Aart Bikf8f5a162017-02-06 15:35:29 -0800414};
415
416// Negates every component in the vector,
417// viz. neg[ x1, .. , xn ] = [ -x1, .. , -xn ].
418class HVecNeg FINAL : public HVecUnaryOperation {
419 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100420 HVecNeg(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800421 HInstruction* input,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100422 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800423 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700424 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100425 : HVecUnaryOperation(allocator, input, packed_type, vector_length, dex_pc) {
Aart Bikd58bc322017-05-01 14:49:18 -0700426 DCHECK(HasConsistentPackedTypes(input, packed_type));
Aart Bikf8f5a162017-02-06 15:35:29 -0800427 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700428
429 bool CanBeMoved() const OVERRIDE { return true; }
430
Aart Bikf8f5a162017-02-06 15:35:29 -0800431 DECLARE_INSTRUCTION(VecNeg);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700432
Artem Serovcced8ba2017-07-19 18:18:09 +0100433 protected:
434 DEFAULT_COPY_CONSTRUCTOR(VecNeg);
Aart Bikf8f5a162017-02-06 15:35:29 -0800435};
436
Aart Bik6daebeb2017-04-03 14:35:41 -0700437// Takes absolute value of every component in the vector,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700438// viz. abs[ x1, .. , xn ] = [ |x1|, .. , |xn| ]
439// for signed operand x.
Aart Bik6daebeb2017-04-03 14:35:41 -0700440class HVecAbs FINAL : public HVecUnaryOperation {
441 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100442 HVecAbs(ArenaAllocator* allocator,
Aart Bik6daebeb2017-04-03 14:35:41 -0700443 HInstruction* input,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100444 DataType::Type packed_type,
Aart Bik6daebeb2017-04-03 14:35:41 -0700445 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700446 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100447 : HVecUnaryOperation(allocator, input, packed_type, vector_length, dex_pc) {
Aart Bikd58bc322017-05-01 14:49:18 -0700448 DCHECK(HasConsistentPackedTypes(input, packed_type));
Aart Bik6daebeb2017-04-03 14:35:41 -0700449 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700450
451 bool CanBeMoved() const OVERRIDE { return true; }
452
Aart Bik6daebeb2017-04-03 14:35:41 -0700453 DECLARE_INSTRUCTION(VecAbs);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700454
Artem Serovcced8ba2017-07-19 18:18:09 +0100455 protected:
456 DEFAULT_COPY_CONSTRUCTOR(VecAbs);
Aart Bik6daebeb2017-04-03 14:35:41 -0700457};
458
Aart Bikf8f5a162017-02-06 15:35:29 -0800459// Bitwise- or boolean-nots every component in the vector,
460// viz. not[ x1, .. , xn ] = [ ~x1, .. , ~xn ], or
461// not[ x1, .. , xn ] = [ !x1, .. , !xn ] for boolean.
462class HVecNot FINAL : public HVecUnaryOperation {
463 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100464 HVecNot(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800465 HInstruction* input,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100466 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800467 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700468 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100469 : HVecUnaryOperation(allocator, input, packed_type, vector_length, dex_pc) {
Aart Bikf8f5a162017-02-06 15:35:29 -0800470 DCHECK(input->IsVecOperation());
Aart Bikf8f5a162017-02-06 15:35:29 -0800471 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700472
473 bool CanBeMoved() const OVERRIDE { return true; }
474
Aart Bikf8f5a162017-02-06 15:35:29 -0800475 DECLARE_INSTRUCTION(VecNot);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700476
Artem Serovcced8ba2017-07-19 18:18:09 +0100477 protected:
478 DEFAULT_COPY_CONSTRUCTOR(VecNot);
Aart Bikf8f5a162017-02-06 15:35:29 -0800479};
480
Aart Bik8de59162017-04-21 09:42:01 -0700481//
482// Definitions of concrete binary vector operations in HIR.
483//
484
Aart Bikf8f5a162017-02-06 15:35:29 -0800485// Adds every component in the two vectors,
486// viz. [ x1, .. , xn ] + [ y1, .. , yn ] = [ x1 + y1, .. , xn + yn ].
487class HVecAdd FINAL : public HVecBinaryOperation {
488 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100489 HVecAdd(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800490 HInstruction* left,
491 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100492 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800493 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700494 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100495 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Aart Bikd58bc322017-05-01 14:49:18 -0700496 DCHECK(HasConsistentPackedTypes(left, packed_type));
497 DCHECK(HasConsistentPackedTypes(right, packed_type));
Aart Bikf8f5a162017-02-06 15:35:29 -0800498 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700499
500 bool CanBeMoved() const OVERRIDE { return true; }
501
Aart Bikf8f5a162017-02-06 15:35:29 -0800502 DECLARE_INSTRUCTION(VecAdd);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700503
Artem Serovcced8ba2017-07-19 18:18:09 +0100504 protected:
505 DEFAULT_COPY_CONSTRUCTOR(VecAdd);
Aart Bikf8f5a162017-02-06 15:35:29 -0800506};
507
Aart Bikf3e61ee2017-04-12 17:09:20 -0700508// Performs halving add on every component in the two vectors, viz.
Aart Bikdbbac8f2017-09-01 13:06:08 -0700509// rounded [ x1, .. , xn ] hradd [ y1, .. , yn ] = [ (x1 + y1 + 1) >> 1, .. , (xn + yn + 1) >> 1 ]
510// truncated [ x1, .. , xn ] hadd [ y1, .. , yn ] = [ (x1 + y1) >> 1, .. , (xn + yn ) >> 1 ]
Aart Bik46b6dbc2017-10-03 11:37:37 -0700511// for either both signed or both unsigned operands x, y.
Aart Bikf3e61ee2017-04-12 17:09:20 -0700512class HVecHalvingAdd FINAL : public HVecBinaryOperation {
513 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100514 HVecHalvingAdd(ArenaAllocator* allocator,
Aart Bikf3e61ee2017-04-12 17:09:20 -0700515 HInstruction* left,
516 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100517 DataType::Type packed_type,
Aart Bikf3e61ee2017-04-12 17:09:20 -0700518 size_t vector_length,
Aart Bikf3e61ee2017-04-12 17:09:20 -0700519 bool is_rounded,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700520 bool is_unsigned,
521 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100522 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Vladimir Markod5d2f2c2017-09-26 12:37:26 +0100523 // The `is_unsigned` flag should be used exclusively with the Int32 or Int64.
524 // This flag is a temporary measure while we do not have the Uint32 and Uint64 data types.
525 DCHECK(!is_unsigned ||
526 packed_type == DataType::Type::kInt32 ||
527 packed_type == DataType::Type::kInt64) << packed_type;
Aart Bikd58bc322017-05-01 14:49:18 -0700528 DCHECK(HasConsistentPackedTypes(left, packed_type));
529 DCHECK(HasConsistentPackedTypes(right, packed_type));
Aart Bikdb14fcf2017-04-25 15:53:58 -0700530 SetPackedFlag<kFieldHAddIsUnsigned>(is_unsigned);
531 SetPackedFlag<kFieldHAddIsRounded>(is_rounded);
Aart Bikf3e61ee2017-04-12 17:09:20 -0700532 }
533
Aart Bikdb14fcf2017-04-25 15:53:58 -0700534 bool IsUnsigned() const { return GetPackedFlag<kFieldHAddIsUnsigned>(); }
535 bool IsRounded() const { return GetPackedFlag<kFieldHAddIsRounded>(); }
Aart Bikf3e61ee2017-04-12 17:09:20 -0700536
Aart Bikb79f4ac2017-07-10 10:10:37 -0700537 bool CanBeMoved() const OVERRIDE { return true; }
538
539 bool InstructionDataEquals(const HInstruction* other) const OVERRIDE {
540 DCHECK(other->IsVecHalvingAdd());
541 const HVecHalvingAdd* o = other->AsVecHalvingAdd();
542 return HVecOperation::InstructionDataEquals(o) &&
543 IsUnsigned() == o->IsUnsigned() &&
544 IsRounded() == o->IsRounded();
545 }
546
Aart Bikf3e61ee2017-04-12 17:09:20 -0700547 DECLARE_INSTRUCTION(VecHalvingAdd);
548
Artem Serovcced8ba2017-07-19 18:18:09 +0100549 protected:
550 DEFAULT_COPY_CONSTRUCTOR(VecHalvingAdd);
551
Aart Bikf3e61ee2017-04-12 17:09:20 -0700552 private:
Aart Bikdb14fcf2017-04-25 15:53:58 -0700553 // Additional packed bits.
554 static constexpr size_t kFieldHAddIsUnsigned = HVecOperation::kNumberOfVectorOpPackedBits;
555 static constexpr size_t kFieldHAddIsRounded = kFieldHAddIsUnsigned + 1;
556 static constexpr size_t kNumberOfHAddPackedBits = kFieldHAddIsRounded + 1;
557 static_assert(kNumberOfHAddPackedBits <= kMaxNumberOfPackedBits, "Too many packed fields.");
Aart Bikf3e61ee2017-04-12 17:09:20 -0700558};
559
Aart Bikf8f5a162017-02-06 15:35:29 -0800560// Subtracts every component in the two vectors,
561// viz. [ x1, .. , xn ] - [ y1, .. , yn ] = [ x1 - y1, .. , xn - yn ].
562class HVecSub FINAL : public HVecBinaryOperation {
563 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100564 HVecSub(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800565 HInstruction* left,
566 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100567 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800568 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700569 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100570 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Aart Bikd58bc322017-05-01 14:49:18 -0700571 DCHECK(HasConsistentPackedTypes(left, packed_type));
572 DCHECK(HasConsistentPackedTypes(right, packed_type));
Aart Bikf8f5a162017-02-06 15:35:29 -0800573 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700574
575 bool CanBeMoved() const OVERRIDE { return true; }
576
Aart Bikf8f5a162017-02-06 15:35:29 -0800577 DECLARE_INSTRUCTION(VecSub);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700578
Artem Serovcced8ba2017-07-19 18:18:09 +0100579 protected:
580 DEFAULT_COPY_CONSTRUCTOR(VecSub);
Aart Bikf8f5a162017-02-06 15:35:29 -0800581};
582
583// Multiplies every component in the two vectors,
584// viz. [ x1, .. , xn ] * [ y1, .. , yn ] = [ x1 * y1, .. , xn * yn ].
585class HVecMul FINAL : public HVecBinaryOperation {
586 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100587 HVecMul(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800588 HInstruction* left,
589 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100590 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800591 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700592 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100593 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Aart Bikd58bc322017-05-01 14:49:18 -0700594 DCHECK(HasConsistentPackedTypes(left, packed_type));
595 DCHECK(HasConsistentPackedTypes(right, packed_type));
Aart Bikf8f5a162017-02-06 15:35:29 -0800596 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700597
598 bool CanBeMoved() const OVERRIDE { return true; }
599
Aart Bikf8f5a162017-02-06 15:35:29 -0800600 DECLARE_INSTRUCTION(VecMul);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700601
Artem Serovcced8ba2017-07-19 18:18:09 +0100602 protected:
603 DEFAULT_COPY_CONSTRUCTOR(VecMul);
Aart Bikf8f5a162017-02-06 15:35:29 -0800604};
605
606// Divides every component in the two vectors,
607// viz. [ x1, .. , xn ] / [ y1, .. , yn ] = [ x1 / y1, .. , xn / yn ].
608class HVecDiv FINAL : public HVecBinaryOperation {
609 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100610 HVecDiv(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800611 HInstruction* left,
612 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100613 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800614 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700615 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100616 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Aart Bikd58bc322017-05-01 14:49:18 -0700617 DCHECK(HasConsistentPackedTypes(left, packed_type));
618 DCHECK(HasConsistentPackedTypes(right, packed_type));
Aart Bikf8f5a162017-02-06 15:35:29 -0800619 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700620
621 bool CanBeMoved() const OVERRIDE { return true; }
622
Aart Bikf8f5a162017-02-06 15:35:29 -0800623 DECLARE_INSTRUCTION(VecDiv);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700624
Artem Serovcced8ba2017-07-19 18:18:09 +0100625 protected:
626 DEFAULT_COPY_CONSTRUCTOR(VecDiv);
Aart Bikf8f5a162017-02-06 15:35:29 -0800627};
628
Aart Bikf3e61ee2017-04-12 17:09:20 -0700629// Takes minimum of every component in the two vectors,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700630// viz. MIN( [ x1, .. , xn ] , [ y1, .. , yn ]) = [ min(x1, y1), .. , min(xn, yn) ]
631// for either both signed or both unsigned operands x, y.
Aart Bikf3e61ee2017-04-12 17:09:20 -0700632class HVecMin FINAL : public HVecBinaryOperation {
633 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100634 HVecMin(ArenaAllocator* allocator,
Aart Bikf3e61ee2017-04-12 17:09:20 -0700635 HInstruction* left,
636 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100637 DataType::Type packed_type,
Aart Bikf3e61ee2017-04-12 17:09:20 -0700638 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700639 bool is_unsigned,
640 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100641 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Vladimir Markod5d2f2c2017-09-26 12:37:26 +0100642 // The `is_unsigned` flag should be used exclusively with the Int32 or Int64.
643 // This flag is a temporary measure while we do not have the Uint32 and Uint64 data types.
644 DCHECK(!is_unsigned ||
645 packed_type == DataType::Type::kInt32 ||
646 packed_type == DataType::Type::kInt64) << packed_type;
Aart Bikd58bc322017-05-01 14:49:18 -0700647 DCHECK(HasConsistentPackedTypes(left, packed_type));
648 DCHECK(HasConsistentPackedTypes(right, packed_type));
Aart Bikc8e93c72017-05-10 10:49:22 -0700649 SetPackedFlag<kFieldMinOpIsUnsigned>(is_unsigned);
Aart Bikf3e61ee2017-04-12 17:09:20 -0700650 }
Aart Bikc8e93c72017-05-10 10:49:22 -0700651
652 bool IsUnsigned() const { return GetPackedFlag<kFieldMinOpIsUnsigned>(); }
653
Aart Bikb79f4ac2017-07-10 10:10:37 -0700654 bool CanBeMoved() const OVERRIDE { return true; }
655
656 bool InstructionDataEquals(const HInstruction* other) const OVERRIDE {
657 DCHECK(other->IsVecMin());
658 const HVecMin* o = other->AsVecMin();
659 return HVecOperation::InstructionDataEquals(o) && IsUnsigned() == o->IsUnsigned();
660 }
661
Aart Bikf3e61ee2017-04-12 17:09:20 -0700662 DECLARE_INSTRUCTION(VecMin);
Aart Bikc8e93c72017-05-10 10:49:22 -0700663
Artem Serovcced8ba2017-07-19 18:18:09 +0100664 protected:
665 DEFAULT_COPY_CONSTRUCTOR(VecMin);
666
Aart Bikf3e61ee2017-04-12 17:09:20 -0700667 private:
Aart Bikc8e93c72017-05-10 10:49:22 -0700668 // Additional packed bits.
669 static constexpr size_t kFieldMinOpIsUnsigned = HVecOperation::kNumberOfVectorOpPackedBits;
670 static constexpr size_t kNumberOfMinOpPackedBits = kFieldMinOpIsUnsigned + 1;
671 static_assert(kNumberOfMinOpPackedBits <= kMaxNumberOfPackedBits, "Too many packed fields.");
Aart Bikf3e61ee2017-04-12 17:09:20 -0700672};
673
674// Takes maximum of every component in the two vectors,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700675// viz. MAX( [ x1, .. , xn ] , [ y1, .. , yn ]) = [ max(x1, y1), .. , max(xn, yn) ]
676// for either both signed or both unsigned operands x, y.
Aart Bikf3e61ee2017-04-12 17:09:20 -0700677class HVecMax FINAL : public HVecBinaryOperation {
678 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100679 HVecMax(ArenaAllocator* allocator,
Aart Bikf3e61ee2017-04-12 17:09:20 -0700680 HInstruction* left,
681 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100682 DataType::Type packed_type,
Aart Bikf3e61ee2017-04-12 17:09:20 -0700683 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700684 bool is_unsigned,
685 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100686 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Vladimir Markod5d2f2c2017-09-26 12:37:26 +0100687 // The `is_unsigned` flag should be used exclusively with the Int32 or Int64.
688 // This flag is a temporary measure while we do not have the Uint32 and Uint64 data types.
689 DCHECK(!is_unsigned ||
690 packed_type == DataType::Type::kInt32 ||
691 packed_type == DataType::Type::kInt64) << packed_type;
Aart Bikd58bc322017-05-01 14:49:18 -0700692 DCHECK(HasConsistentPackedTypes(left, packed_type));
693 DCHECK(HasConsistentPackedTypes(right, packed_type));
Aart Bikc8e93c72017-05-10 10:49:22 -0700694 SetPackedFlag<kFieldMaxOpIsUnsigned>(is_unsigned);
Aart Bikf3e61ee2017-04-12 17:09:20 -0700695 }
Aart Bikc8e93c72017-05-10 10:49:22 -0700696
697 bool IsUnsigned() const { return GetPackedFlag<kFieldMaxOpIsUnsigned>(); }
698
Aart Bikb79f4ac2017-07-10 10:10:37 -0700699 bool CanBeMoved() const OVERRIDE { return true; }
700
701 bool InstructionDataEquals(const HInstruction* other) const OVERRIDE {
702 DCHECK(other->IsVecMax());
703 const HVecMax* o = other->AsVecMax();
704 return HVecOperation::InstructionDataEquals(o) && IsUnsigned() == o->IsUnsigned();
705 }
706
Aart Bikf3e61ee2017-04-12 17:09:20 -0700707 DECLARE_INSTRUCTION(VecMax);
Aart Bikc8e93c72017-05-10 10:49:22 -0700708
Artem Serovcced8ba2017-07-19 18:18:09 +0100709 protected:
710 DEFAULT_COPY_CONSTRUCTOR(VecMax);
711
Aart Bikf3e61ee2017-04-12 17:09:20 -0700712 private:
Aart Bikc8e93c72017-05-10 10:49:22 -0700713 // Additional packed bits.
714 static constexpr size_t kFieldMaxOpIsUnsigned = HVecOperation::kNumberOfVectorOpPackedBits;
715 static constexpr size_t kNumberOfMaxOpPackedBits = kFieldMaxOpIsUnsigned + 1;
716 static_assert(kNumberOfMaxOpPackedBits <= kMaxNumberOfPackedBits, "Too many packed fields.");
Aart Bikf3e61ee2017-04-12 17:09:20 -0700717};
718
Aart Bikf8f5a162017-02-06 15:35:29 -0800719// Bitwise-ands every component in the two vectors,
720// viz. [ x1, .. , xn ] & [ y1, .. , yn ] = [ x1 & y1, .. , xn & yn ].
721class HVecAnd FINAL : public HVecBinaryOperation {
722 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100723 HVecAnd(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800724 HInstruction* left,
725 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100726 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800727 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700728 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100729 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Aart Bikf8f5a162017-02-06 15:35:29 -0800730 DCHECK(left->IsVecOperation() && right->IsVecOperation());
Aart Bikf8f5a162017-02-06 15:35:29 -0800731 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700732
733 bool CanBeMoved() const OVERRIDE { return true; }
734
Aart Bikf8f5a162017-02-06 15:35:29 -0800735 DECLARE_INSTRUCTION(VecAnd);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700736
Artem Serovcced8ba2017-07-19 18:18:09 +0100737 protected:
738 DEFAULT_COPY_CONSTRUCTOR(VecAnd);
Aart Bikf8f5a162017-02-06 15:35:29 -0800739};
740
741// Bitwise-and-nots every component in the two vectors,
742// viz. [ x1, .. , xn ] and-not [ y1, .. , yn ] = [ ~x1 & y1, .. , ~xn & yn ].
743class HVecAndNot FINAL : public HVecBinaryOperation {
744 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100745 HVecAndNot(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800746 HInstruction* left,
747 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100748 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800749 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700750 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100751 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Aart Bikf8f5a162017-02-06 15:35:29 -0800752 DCHECK(left->IsVecOperation() && right->IsVecOperation());
Aart Bikf8f5a162017-02-06 15:35:29 -0800753 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700754
755 bool CanBeMoved() const OVERRIDE { return true; }
756
Aart Bikf8f5a162017-02-06 15:35:29 -0800757 DECLARE_INSTRUCTION(VecAndNot);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700758
Artem Serovcced8ba2017-07-19 18:18:09 +0100759 protected:
760 DEFAULT_COPY_CONSTRUCTOR(VecAndNot);
Aart Bikf8f5a162017-02-06 15:35:29 -0800761};
762
763// Bitwise-ors every component in the two vectors,
764// viz. [ x1, .. , xn ] | [ y1, .. , yn ] = [ x1 | y1, .. , xn | yn ].
765class HVecOr FINAL : public HVecBinaryOperation {
766 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100767 HVecOr(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800768 HInstruction* left,
769 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100770 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800771 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700772 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100773 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Aart Bikf8f5a162017-02-06 15:35:29 -0800774 DCHECK(left->IsVecOperation() && right->IsVecOperation());
Aart Bikf8f5a162017-02-06 15:35:29 -0800775 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700776
777 bool CanBeMoved() const OVERRIDE { return true; }
778
Aart Bikf8f5a162017-02-06 15:35:29 -0800779 DECLARE_INSTRUCTION(VecOr);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700780
Artem Serovcced8ba2017-07-19 18:18:09 +0100781 protected:
782 DEFAULT_COPY_CONSTRUCTOR(VecOr);
Aart Bikf8f5a162017-02-06 15:35:29 -0800783};
784
785// Bitwise-xors every component in the two vectors,
786// viz. [ x1, .. , xn ] ^ [ y1, .. , yn ] = [ x1 ^ y1, .. , xn ^ yn ].
787class HVecXor FINAL : public HVecBinaryOperation {
788 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100789 HVecXor(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800790 HInstruction* left,
791 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100792 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800793 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700794 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100795 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Aart Bikf8f5a162017-02-06 15:35:29 -0800796 DCHECK(left->IsVecOperation() && right->IsVecOperation());
Aart Bikf8f5a162017-02-06 15:35:29 -0800797 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700798
799 bool CanBeMoved() const OVERRIDE { return true; }
800
Aart Bikf8f5a162017-02-06 15:35:29 -0800801 DECLARE_INSTRUCTION(VecXor);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700802
Artem Serovcced8ba2017-07-19 18:18:09 +0100803 protected:
804 DEFAULT_COPY_CONSTRUCTOR(VecXor);
Aart Bikf8f5a162017-02-06 15:35:29 -0800805};
806
807// Logically shifts every component in the vector left by the given distance,
808// viz. [ x1, .. , xn ] << d = [ x1 << d, .. , xn << d ].
809class HVecShl FINAL : public HVecBinaryOperation {
810 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100811 HVecShl(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800812 HInstruction* left,
813 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100814 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800815 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700816 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100817 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Aart Bikd58bc322017-05-01 14:49:18 -0700818 DCHECK(HasConsistentPackedTypes(left, packed_type));
Aart Bikf8f5a162017-02-06 15:35:29 -0800819 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700820
821 bool CanBeMoved() const OVERRIDE { return true; }
822
Aart Bikf8f5a162017-02-06 15:35:29 -0800823 DECLARE_INSTRUCTION(VecShl);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700824
Artem Serovcced8ba2017-07-19 18:18:09 +0100825 protected:
826 DEFAULT_COPY_CONSTRUCTOR(VecShl);
Aart Bikf8f5a162017-02-06 15:35:29 -0800827};
828
829// Arithmetically shifts every component in the vector right by the given distance,
830// viz. [ x1, .. , xn ] >> d = [ x1 >> d, .. , xn >> d ].
831class HVecShr FINAL : public HVecBinaryOperation {
832 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100833 HVecShr(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800834 HInstruction* left,
835 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100836 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800837 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700838 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100839 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Aart Bikd58bc322017-05-01 14:49:18 -0700840 DCHECK(HasConsistentPackedTypes(left, packed_type));
Aart Bikf8f5a162017-02-06 15:35:29 -0800841 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700842
843 bool CanBeMoved() const OVERRIDE { return true; }
844
Aart Bikf8f5a162017-02-06 15:35:29 -0800845 DECLARE_INSTRUCTION(VecShr);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700846
Artem Serovcced8ba2017-07-19 18:18:09 +0100847 protected:
848 DEFAULT_COPY_CONSTRUCTOR(VecShr);
Aart Bikf8f5a162017-02-06 15:35:29 -0800849};
850
851// Logically shifts every component in the vector right by the given distance,
852// viz. [ x1, .. , xn ] >>> d = [ x1 >>> d, .. , xn >>> d ].
853class HVecUShr FINAL : public HVecBinaryOperation {
854 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100855 HVecUShr(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800856 HInstruction* left,
857 HInstruction* right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100858 DataType::Type packed_type,
Aart Bikf8f5a162017-02-06 15:35:29 -0800859 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700860 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100861 : HVecBinaryOperation(allocator, left, right, packed_type, vector_length, dex_pc) {
Aart Bikd58bc322017-05-01 14:49:18 -0700862 DCHECK(HasConsistentPackedTypes(left, packed_type));
Aart Bikf8f5a162017-02-06 15:35:29 -0800863 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700864
865 bool CanBeMoved() const OVERRIDE { return true; }
866
Aart Bikf8f5a162017-02-06 15:35:29 -0800867 DECLARE_INSTRUCTION(VecUShr);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700868
Artem Serovcced8ba2017-07-19 18:18:09 +0100869 protected:
870 DEFAULT_COPY_CONSTRUCTOR(VecUShr);
Aart Bikf8f5a162017-02-06 15:35:29 -0800871};
872
Aart Bik8de59162017-04-21 09:42:01 -0700873//
874// Definitions of concrete miscellaneous vector operations in HIR.
875//
876
877// Assigns the given scalar elements to a vector,
Aart Bikdbbac8f2017-09-01 13:06:08 -0700878// viz. set( array(x1, .. , xn) ) = [ x1, .. , xn ] if n == m,
879// set( array(x1, .. , xm) ) = [ x1, .. , xm, 0, .. , 0 ] if m < n.
Aart Bik8de59162017-04-21 09:42:01 -0700880class HVecSetScalars FINAL : public HVecOperation {
Aart Bik0148de42017-09-05 09:25:01 -0700881 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100882 HVecSetScalars(ArenaAllocator* allocator,
Aart Bik5e3afa92017-09-20 14:11:11 -0700883 HInstruction* scalars[],
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100884 DataType::Type packed_type,
Aart Bik8de59162017-04-21 09:42:01 -0700885 size_t vector_length,
Aart Bik0148de42017-09-05 09:25:01 -0700886 size_t number_of_scalars,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700887 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100888 : HVecOperation(allocator,
Aart Bik8de59162017-04-21 09:42:01 -0700889 packed_type,
890 SideEffects::None(),
Aart Bik0148de42017-09-05 09:25:01 -0700891 number_of_scalars,
Aart Bik8de59162017-04-21 09:42:01 -0700892 vector_length,
893 dex_pc) {
Aart Bik0148de42017-09-05 09:25:01 -0700894 for (size_t i = 0; i < number_of_scalars; i++) {
Aart Bik2dd7b672017-12-07 11:11:22 -0800895 DCHECK(!ReturnsSIMDValue(scalars[i]));
Aart Bik8de59162017-04-21 09:42:01 -0700896 SetRawInputAt(0, scalars[i]);
897 }
898 }
Aart Bikb79f4ac2017-07-10 10:10:37 -0700899
900 // Setting scalars needs to stay in place, since SIMD registers are not
901 // kept alive across vector loop boundaries (yet).
902 bool CanBeMoved() const OVERRIDE { return false; }
903
Aart Bik8de59162017-04-21 09:42:01 -0700904 DECLARE_INSTRUCTION(VecSetScalars);
Aart Bikb79f4ac2017-07-10 10:10:37 -0700905
Artem Serovcced8ba2017-07-19 18:18:09 +0100906 protected:
907 DEFAULT_COPY_CONSTRUCTOR(VecSetScalars);
Aart Bik8de59162017-04-21 09:42:01 -0700908};
909
Aart Bikdbbac8f2017-09-01 13:06:08 -0700910// Multiplies every component in the two vectors, adds the result vector to the accumulator vector,
911// viz. [ a1, .. , an ] + [ x1, .. , xn ] * [ y1, .. , yn ] = [ a1 + x1 * y1, .. , an + xn * yn ].
Artem Serovf34dd202017-04-10 17:41:46 +0100912class HVecMultiplyAccumulate FINAL : public HVecOperation {
913 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100914 HVecMultiplyAccumulate(ArenaAllocator* allocator,
Artem Serovf34dd202017-04-10 17:41:46 +0100915 InstructionKind op,
916 HInstruction* accumulator,
917 HInstruction* mul_left,
918 HInstruction* mul_right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100919 DataType::Type packed_type,
Artem Serovf34dd202017-04-10 17:41:46 +0100920 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700921 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100922 : HVecOperation(allocator,
Artem Serovf34dd202017-04-10 17:41:46 +0100923 packed_type,
924 SideEffects::None(),
Aart Bik8de59162017-04-21 09:42:01 -0700925 /* number_of_inputs */ 3,
Artem Serovf34dd202017-04-10 17:41:46 +0100926 vector_length,
927 dex_pc),
928 op_kind_(op) {
929 DCHECK(op == InstructionKind::kAdd || op == InstructionKind::kSub);
Aart Bikd58bc322017-05-01 14:49:18 -0700930 DCHECK(HasConsistentPackedTypes(accumulator, packed_type));
931 DCHECK(HasConsistentPackedTypes(mul_left, packed_type));
932 DCHECK(HasConsistentPackedTypes(mul_right, packed_type));
Aart Bikdbbac8f2017-09-01 13:06:08 -0700933 SetRawInputAt(0, accumulator);
934 SetRawInputAt(1, mul_left);
935 SetRawInputAt(2, mul_right);
Artem Serovf34dd202017-04-10 17:41:46 +0100936 }
937
Nicolas Geoffray9858bf72017-07-08 12:34:55 +0000938 bool CanBeMoved() const OVERRIDE { return true; }
939
Artem Serovf34dd202017-04-10 17:41:46 +0100940 bool InstructionDataEquals(const HInstruction* other) const OVERRIDE {
Aart Bikb79f4ac2017-07-10 10:10:37 -0700941 DCHECK(other->IsVecMultiplyAccumulate());
942 const HVecMultiplyAccumulate* o = other->AsVecMultiplyAccumulate();
943 return HVecOperation::InstructionDataEquals(o) && GetOpKind() == o->GetOpKind();
Artem Serovf34dd202017-04-10 17:41:46 +0100944 }
945
946 InstructionKind GetOpKind() const { return op_kind_; }
947
948 DECLARE_INSTRUCTION(VecMultiplyAccumulate);
949
Artem Serovcced8ba2017-07-19 18:18:09 +0100950 protected:
951 DEFAULT_COPY_CONSTRUCTOR(VecMultiplyAccumulate);
952
Artem Serovf34dd202017-04-10 17:41:46 +0100953 private:
954 // Indicates if this is a MADD or MSUB.
955 const InstructionKind op_kind_;
Artem Serovf34dd202017-04-10 17:41:46 +0100956};
957
Aart Bikdbbac8f2017-09-01 13:06:08 -0700958// Takes the absolute difference of two vectors, and adds the results to
959// same-precision or wider-precision components in the accumulator,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700960// viz. SAD([ a1, .. , am ], [ x1, .. , xn ], [ y1, .. , yn ]) =
Aart Bikdbbac8f2017-09-01 13:06:08 -0700961// [ a1 + sum abs(xi-yi), .. , am + sum abs(xj-yj) ],
Aart Bik46b6dbc2017-10-03 11:37:37 -0700962// for m <= n, non-overlapping sums, and signed operands x, y.
Aart Bikdbbac8f2017-09-01 13:06:08 -0700963class HVecSADAccumulate FINAL : public HVecOperation {
964 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100965 HVecSADAccumulate(ArenaAllocator* allocator,
Aart Bikdbbac8f2017-09-01 13:06:08 -0700966 HInstruction* accumulator,
967 HInstruction* sad_left,
968 HInstruction* sad_right,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +0100969 DataType::Type packed_type,
Aart Bikdbbac8f2017-09-01 13:06:08 -0700970 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -0700971 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100972 : HVecOperation(allocator,
Aart Bikdbbac8f2017-09-01 13:06:08 -0700973 packed_type,
974 SideEffects::None(),
975 /* number_of_inputs */ 3,
976 vector_length,
977 dex_pc) {
978 DCHECK(HasConsistentPackedTypes(accumulator, packed_type));
979 DCHECK(sad_left->IsVecOperation());
980 DCHECK(sad_right->IsVecOperation());
Vladimir Marko61b92282017-10-11 13:23:17 +0100981 DCHECK_EQ(ToSignedType(sad_left->AsVecOperation()->GetPackedType()),
982 ToSignedType(sad_right->AsVecOperation()->GetPackedType()));
Aart Bikdbbac8f2017-09-01 13:06:08 -0700983 SetRawInputAt(0, accumulator);
984 SetRawInputAt(1, sad_left);
985 SetRawInputAt(2, sad_right);
986 }
987
988 DECLARE_INSTRUCTION(VecSADAccumulate);
989
Artem Serovcced8ba2017-07-19 18:18:09 +0100990 protected:
991 DEFAULT_COPY_CONSTRUCTOR(VecSADAccumulate);
Aart Bikdbbac8f2017-09-01 13:06:08 -0700992};
993
Aart Bikf8f5a162017-02-06 15:35:29 -0800994// Loads a vector from memory, viz. load(mem, 1)
995// yield the vector [ mem(1), .. , mem(n) ].
996class HVecLoad FINAL : public HVecMemoryOperation {
997 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +0100998 HVecLoad(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -0800999 HInstruction* base,
1000 HInstruction* index,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +01001001 DataType::Type packed_type,
Vladimir Markod5d2f2c2017-09-26 12:37:26 +01001002 SideEffects side_effects,
Aart Bikf8f5a162017-02-06 15:35:29 -08001003 size_t vector_length,
Aart Bikdb14fcf2017-04-25 15:53:58 -07001004 bool is_string_char_at,
Aart Bik46b6dbc2017-10-03 11:37:37 -07001005 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +01001006 : HVecMemoryOperation(allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -08001007 packed_type,
Vladimir Markod5d2f2c2017-09-26 12:37:26 +01001008 side_effects,
Aart Bik8de59162017-04-21 09:42:01 -07001009 /* number_of_inputs */ 2,
Aart Bikf8f5a162017-02-06 15:35:29 -08001010 vector_length,
1011 dex_pc) {
1012 SetRawInputAt(0, base);
1013 SetRawInputAt(1, index);
Aart Bikdb14fcf2017-04-25 15:53:58 -07001014 SetPackedFlag<kFieldIsStringCharAt>(is_string_char_at);
Aart Bikf8f5a162017-02-06 15:35:29 -08001015 }
Aart Bikdb14fcf2017-04-25 15:53:58 -07001016
1017 bool IsStringCharAt() const { return GetPackedFlag<kFieldIsStringCharAt>(); }
1018
Aart Bikb79f4ac2017-07-10 10:10:37 -07001019 bool CanBeMoved() const OVERRIDE { return true; }
1020
1021 bool InstructionDataEquals(const HInstruction* other) const OVERRIDE {
1022 DCHECK(other->IsVecLoad());
1023 const HVecLoad* o = other->AsVecLoad();
1024 return HVecMemoryOperation::InstructionDataEquals(o) && IsStringCharAt() == o->IsStringCharAt();
1025 }
1026
1027 DECLARE_INSTRUCTION(VecLoad);
1028
Artem Serovcced8ba2017-07-19 18:18:09 +01001029 protected:
1030 DEFAULT_COPY_CONSTRUCTOR(VecLoad);
1031
Aart Bikf8f5a162017-02-06 15:35:29 -08001032 private:
Aart Bikdb14fcf2017-04-25 15:53:58 -07001033 // Additional packed bits.
1034 static constexpr size_t kFieldIsStringCharAt = HVecOperation::kNumberOfVectorOpPackedBits;
1035 static constexpr size_t kNumberOfVecLoadPackedBits = kFieldIsStringCharAt + 1;
1036 static_assert(kNumberOfVecLoadPackedBits <= kMaxNumberOfPackedBits, "Too many packed fields.");
Aart Bikf8f5a162017-02-06 15:35:29 -08001037};
1038
1039// Stores a vector to memory, viz. store(m, 1, [x1, .. , xn] )
1040// sets mem(1) = x1, .. , mem(n) = xn.
1041class HVecStore FINAL : public HVecMemoryOperation {
1042 public:
Vladimir Markoe764d2e2017-10-05 14:35:55 +01001043 HVecStore(ArenaAllocator* allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -08001044 HInstruction* base,
1045 HInstruction* index,
1046 HInstruction* value,
Vladimir Marko0ebe0d82017-09-21 22:50:39 +01001047 DataType::Type packed_type,
Vladimir Markod5d2f2c2017-09-26 12:37:26 +01001048 SideEffects side_effects,
Aart Bikf8f5a162017-02-06 15:35:29 -08001049 size_t vector_length,
Aart Bik46b6dbc2017-10-03 11:37:37 -07001050 uint32_t dex_pc)
Vladimir Markoe764d2e2017-10-05 14:35:55 +01001051 : HVecMemoryOperation(allocator,
Aart Bikf8f5a162017-02-06 15:35:29 -08001052 packed_type,
Vladimir Markod5d2f2c2017-09-26 12:37:26 +01001053 side_effects,
Aart Bik8de59162017-04-21 09:42:01 -07001054 /* number_of_inputs */ 3,
Aart Bikf8f5a162017-02-06 15:35:29 -08001055 vector_length,
1056 dex_pc) {
Aart Bikd58bc322017-05-01 14:49:18 -07001057 DCHECK(HasConsistentPackedTypes(value, packed_type));
Aart Bikf8f5a162017-02-06 15:35:29 -08001058 SetRawInputAt(0, base);
1059 SetRawInputAt(1, index);
1060 SetRawInputAt(2, value);
1061 }
Aart Bikb79f4ac2017-07-10 10:10:37 -07001062
1063 // A store needs to stay in place.
1064 bool CanBeMoved() const OVERRIDE { return false; }
1065
Aart Bikf8f5a162017-02-06 15:35:29 -08001066 DECLARE_INSTRUCTION(VecStore);
Aart Bikb79f4ac2017-07-10 10:10:37 -07001067
Artem Serovcced8ba2017-07-19 18:18:09 +01001068 protected:
1069 DEFAULT_COPY_CONSTRUCTOR(VecStore)
Aart Bikf8f5a162017-02-06 15:35:29 -08001070};
1071
1072} // namespace art
1073
1074#endif // ART_COMPILER_OPTIMIZING_NODES_VECTOR_H_