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Elliott Hughes2faa5f12012-01-30 14:42:07 -08001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070016
Ian Rogers2c8f6532011-09-02 17:16:34 -070017#include "assembler_x86.h"
18
Elliott Hughes1aa246d2012-12-13 09:29:36 -080019#include "base/casts.h"
Ian Rogers166db042013-07-26 12:05:57 -070020#include "entrypoints/quick/quick_entrypoints.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070021#include "memory_region.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070022#include "thread.h"
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070023
Carl Shapiro6b6b5f02011-06-21 15:05:09 -070024namespace art {
Ian Rogers2c8f6532011-09-02 17:16:34 -070025namespace x86 {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070026
Ian Rogersb033c752011-07-20 12:22:35 -070027std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
28 return os << "XMM" << static_cast<int>(reg);
29}
30
31std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
32 return os << "ST" << static_cast<int>(reg);
33}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070034
Ian Rogers2c8f6532011-09-02 17:16:34 -070035void X86Assembler::call(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070036 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
37 EmitUint8(0xFF);
38 EmitRegisterOperand(2, reg);
39}
40
41
Ian Rogers2c8f6532011-09-02 17:16:34 -070042void X86Assembler::call(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070043 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
44 EmitUint8(0xFF);
45 EmitOperand(2, address);
46}
47
48
Ian Rogers2c8f6532011-09-02 17:16:34 -070049void X86Assembler::call(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070050 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
51 EmitUint8(0xE8);
52 static const int kSize = 5;
Nicolas Geoffray1cf95282014-12-12 19:22:03 +000053 // Offset by one because we already have emitted the opcode.
54 EmitLabel(label, kSize - 1);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070055}
56
57
Nicolas Geoffray8ccc3f52014-03-19 10:34:11 +000058void X86Assembler::call(const ExternalLabel& label) {
59 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
60 intptr_t call_start = buffer_.GetPosition();
61 EmitUint8(0xE8);
62 EmitInt32(label.address());
63 static const intptr_t kCallExternalLabelSize = 5;
64 DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
65}
66
67
Ian Rogers2c8f6532011-09-02 17:16:34 -070068void X86Assembler::pushl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
70 EmitUint8(0x50 + reg);
71}
72
73
Ian Rogers2c8f6532011-09-02 17:16:34 -070074void X86Assembler::pushl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070075 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
76 EmitUint8(0xFF);
77 EmitOperand(6, address);
78}
79
80
Ian Rogers2c8f6532011-09-02 17:16:34 -070081void X86Assembler::pushl(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070082 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Ian Rogers44fb0d02012-03-23 16:46:24 -070083 if (imm.is_int8()) {
84 EmitUint8(0x6A);
85 EmitUint8(imm.value() & 0xFF);
86 } else {
87 EmitUint8(0x68);
88 EmitImmediate(imm);
89 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070090}
91
92
Ian Rogers2c8f6532011-09-02 17:16:34 -070093void X86Assembler::popl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070094 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
95 EmitUint8(0x58 + reg);
96}
97
98
Ian Rogers2c8f6532011-09-02 17:16:34 -070099void X86Assembler::popl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700100 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
101 EmitUint8(0x8F);
102 EmitOperand(0, address);
103}
104
105
Ian Rogers2c8f6532011-09-02 17:16:34 -0700106void X86Assembler::movl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700107 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
108 EmitUint8(0xB8 + dst);
109 EmitImmediate(imm);
110}
111
112
Ian Rogers2c8f6532011-09-02 17:16:34 -0700113void X86Assembler::movl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700114 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
115 EmitUint8(0x89);
116 EmitRegisterOperand(src, dst);
117}
118
119
Ian Rogers2c8f6532011-09-02 17:16:34 -0700120void X86Assembler::movl(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
122 EmitUint8(0x8B);
123 EmitOperand(dst, src);
124}
125
126
Ian Rogers2c8f6532011-09-02 17:16:34 -0700127void X86Assembler::movl(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700128 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
129 EmitUint8(0x89);
130 EmitOperand(src, dst);
131}
132
133
Ian Rogers2c8f6532011-09-02 17:16:34 -0700134void X86Assembler::movl(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700135 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
136 EmitUint8(0xC7);
137 EmitOperand(0, dst);
138 EmitImmediate(imm);
139}
140
Ian Rogersbdb03912011-09-14 00:55:44 -0700141void X86Assembler::movl(const Address& dst, Label* lbl) {
142 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
143 EmitUint8(0xC7);
144 EmitOperand(0, dst);
145 EmitLabel(lbl, dst.length_ + 5);
146}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700147
Mark Mendell7a08fb52015-07-15 14:09:35 -0400148void X86Assembler::movntl(const Address& dst, Register src) {
149 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
150 EmitUint8(0x0F);
151 EmitUint8(0xC3);
152 EmitOperand(src, dst);
153}
154
Mark Mendell09ed1a32015-03-25 08:30:06 -0400155void X86Assembler::bswapl(Register dst) {
156 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
157 EmitUint8(0x0F);
158 EmitUint8(0xC8 + dst);
159}
160
Mark Mendellbcee0922015-09-15 21:45:01 -0400161void X86Assembler::bsfl(Register dst, Register src) {
162 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
163 EmitUint8(0x0F);
164 EmitUint8(0xBC);
165 EmitRegisterOperand(dst, src);
166}
167
168void X86Assembler::bsfl(Register dst, const Address& src) {
169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
170 EmitUint8(0x0F);
171 EmitUint8(0xBC);
172 EmitOperand(dst, src);
173}
174
Mark Mendell8ae3ffb2015-08-12 21:16:41 -0400175void X86Assembler::bsrl(Register dst, Register src) {
176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
177 EmitUint8(0x0F);
178 EmitUint8(0xBD);
179 EmitRegisterOperand(dst, src);
180}
181
182void X86Assembler::bsrl(Register dst, const Address& src) {
183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
184 EmitUint8(0x0F);
185 EmitUint8(0xBD);
186 EmitOperand(dst, src);
187}
188
Aart Bikc39dac12016-01-21 08:59:48 -0800189void X86Assembler::popcntl(Register dst, Register src) {
190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
191 EmitUint8(0xF3);
192 EmitUint8(0x0F);
193 EmitUint8(0xB8);
194 EmitRegisterOperand(dst, src);
195}
196
197void X86Assembler::popcntl(Register dst, const Address& src) {
198 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
199 EmitUint8(0xF3);
200 EmitUint8(0x0F);
201 EmitUint8(0xB8);
202 EmitOperand(dst, src);
203}
204
Ian Rogers2c8f6532011-09-02 17:16:34 -0700205void X86Assembler::movzxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700206 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
207 EmitUint8(0x0F);
208 EmitUint8(0xB6);
209 EmitRegisterOperand(dst, src);
210}
211
212
Ian Rogers2c8f6532011-09-02 17:16:34 -0700213void X86Assembler::movzxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700214 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
215 EmitUint8(0x0F);
216 EmitUint8(0xB6);
217 EmitOperand(dst, src);
218}
219
220
Ian Rogers2c8f6532011-09-02 17:16:34 -0700221void X86Assembler::movsxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700222 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
223 EmitUint8(0x0F);
224 EmitUint8(0xBE);
225 EmitRegisterOperand(dst, src);
226}
227
228
Ian Rogers2c8f6532011-09-02 17:16:34 -0700229void X86Assembler::movsxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700230 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
231 EmitUint8(0x0F);
232 EmitUint8(0xBE);
233 EmitOperand(dst, src);
234}
235
236
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700237void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700238 LOG(FATAL) << "Use movzxb or movsxb instead.";
239}
240
241
Ian Rogers2c8f6532011-09-02 17:16:34 -0700242void X86Assembler::movb(const Address& dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700243 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
244 EmitUint8(0x88);
245 EmitOperand(src, dst);
246}
247
248
Ian Rogers2c8f6532011-09-02 17:16:34 -0700249void X86Assembler::movb(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700250 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
251 EmitUint8(0xC6);
252 EmitOperand(EAX, dst);
253 CHECK(imm.is_int8());
254 EmitUint8(imm.value() & 0xFF);
255}
256
257
Ian Rogers2c8f6532011-09-02 17:16:34 -0700258void X86Assembler::movzxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700259 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
260 EmitUint8(0x0F);
261 EmitUint8(0xB7);
262 EmitRegisterOperand(dst, src);
263}
264
265
Ian Rogers2c8f6532011-09-02 17:16:34 -0700266void X86Assembler::movzxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700267 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
268 EmitUint8(0x0F);
269 EmitUint8(0xB7);
270 EmitOperand(dst, src);
271}
272
273
Ian Rogers2c8f6532011-09-02 17:16:34 -0700274void X86Assembler::movsxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700275 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
276 EmitUint8(0x0F);
277 EmitUint8(0xBF);
278 EmitRegisterOperand(dst, src);
279}
280
281
Ian Rogers2c8f6532011-09-02 17:16:34 -0700282void X86Assembler::movsxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700283 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
284 EmitUint8(0x0F);
285 EmitUint8(0xBF);
286 EmitOperand(dst, src);
287}
288
289
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700290void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700291 LOG(FATAL) << "Use movzxw or movsxw instead.";
292}
293
294
Ian Rogers2c8f6532011-09-02 17:16:34 -0700295void X86Assembler::movw(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700296 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
297 EmitOperandSizeOverride();
298 EmitUint8(0x89);
299 EmitOperand(src, dst);
300}
301
302
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100303void X86Assembler::movw(const Address& dst, const Immediate& imm) {
304 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
305 EmitOperandSizeOverride();
306 EmitUint8(0xC7);
307 EmitOperand(0, dst);
Nicolas Geoffrayb6e72062014-10-07 14:54:48 +0100308 CHECK(imm.is_uint16() || imm.is_int16());
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100309 EmitUint8(imm.value() & 0xFF);
310 EmitUint8(imm.value() >> 8);
311}
312
313
Ian Rogers2c8f6532011-09-02 17:16:34 -0700314void X86Assembler::leal(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700315 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
316 EmitUint8(0x8D);
317 EmitOperand(dst, src);
318}
319
320
Ian Rogers2c8f6532011-09-02 17:16:34 -0700321void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700322 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
323 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700324 EmitUint8(0x40 + condition);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700325 EmitRegisterOperand(dst, src);
326}
327
328
Mark Mendellabdac472016-02-12 13:49:03 -0500329void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
330 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
331 EmitUint8(0x0F);
332 EmitUint8(0x40 + condition);
333 EmitOperand(dst, src);
334}
335
336
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000337void X86Assembler::setb(Condition condition, Register dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700338 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
339 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700340 EmitUint8(0x90 + condition);
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000341 EmitOperand(0, Operand(dst));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700342}
343
344
Nicolas Geoffray7fb49da2014-10-06 09:12:41 +0100345void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
346 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
347 EmitUint8(0x0F);
348 EmitUint8(0x28);
349 EmitXmmRegisterOperand(dst, src);
350}
351
352
Aart Bikc7782262017-01-13 16:20:08 -0800353void X86Assembler::movaps(XmmRegister dst, const Address& src) {
354 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
355 EmitUint8(0x0F);
356 EmitUint8(0x28);
357 EmitOperand(dst, src);
358}
359
360
361void X86Assembler::movups(XmmRegister dst, const Address& src) {
362 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
363 EmitUint8(0x0F);
364 EmitUint8(0x10);
365 EmitOperand(dst, src);
366}
367
368
369void X86Assembler::movaps(const Address& dst, XmmRegister src) {
370 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
371 EmitUint8(0x0F);
372 EmitUint8(0x29);
373 EmitOperand(src, dst);
374}
375
376
377void X86Assembler::movups(const Address& dst, XmmRegister src) {
378 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
379 EmitUint8(0x0F);
380 EmitUint8(0x11);
381 EmitOperand(src, dst);
382}
383
384
Ian Rogers2c8f6532011-09-02 17:16:34 -0700385void X86Assembler::movss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700386 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
387 EmitUint8(0xF3);
388 EmitUint8(0x0F);
389 EmitUint8(0x10);
390 EmitOperand(dst, src);
391}
392
393
Ian Rogers2c8f6532011-09-02 17:16:34 -0700394void X86Assembler::movss(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700395 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
396 EmitUint8(0xF3);
397 EmitUint8(0x0F);
398 EmitUint8(0x11);
399 EmitOperand(src, dst);
400}
401
402
Ian Rogers2c8f6532011-09-02 17:16:34 -0700403void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700404 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
405 EmitUint8(0xF3);
406 EmitUint8(0x0F);
407 EmitUint8(0x11);
408 EmitXmmRegisterOperand(src, dst);
409}
410
411
Ian Rogers2c8f6532011-09-02 17:16:34 -0700412void X86Assembler::movd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700413 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
414 EmitUint8(0x66);
415 EmitUint8(0x0F);
416 EmitUint8(0x6E);
417 EmitOperand(dst, Operand(src));
418}
419
420
Ian Rogers2c8f6532011-09-02 17:16:34 -0700421void X86Assembler::movd(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700422 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
423 EmitUint8(0x66);
424 EmitUint8(0x0F);
425 EmitUint8(0x7E);
426 EmitOperand(src, Operand(dst));
427}
428
429
Ian Rogers2c8f6532011-09-02 17:16:34 -0700430void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700431 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
432 EmitUint8(0xF3);
433 EmitUint8(0x0F);
434 EmitUint8(0x58);
435 EmitXmmRegisterOperand(dst, src);
436}
437
438
Ian Rogers2c8f6532011-09-02 17:16:34 -0700439void X86Assembler::addss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700440 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
441 EmitUint8(0xF3);
442 EmitUint8(0x0F);
443 EmitUint8(0x58);
444 EmitOperand(dst, src);
445}
446
447
Ian Rogers2c8f6532011-09-02 17:16:34 -0700448void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700449 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
450 EmitUint8(0xF3);
451 EmitUint8(0x0F);
452 EmitUint8(0x5C);
453 EmitXmmRegisterOperand(dst, src);
454}
455
456
Ian Rogers2c8f6532011-09-02 17:16:34 -0700457void X86Assembler::subss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700458 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
459 EmitUint8(0xF3);
460 EmitUint8(0x0F);
461 EmitUint8(0x5C);
462 EmitOperand(dst, src);
463}
464
465
Ian Rogers2c8f6532011-09-02 17:16:34 -0700466void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700467 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
468 EmitUint8(0xF3);
469 EmitUint8(0x0F);
470 EmitUint8(0x59);
471 EmitXmmRegisterOperand(dst, src);
472}
473
474
Ian Rogers2c8f6532011-09-02 17:16:34 -0700475void X86Assembler::mulss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700476 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
477 EmitUint8(0xF3);
478 EmitUint8(0x0F);
479 EmitUint8(0x59);
480 EmitOperand(dst, src);
481}
482
483
Ian Rogers2c8f6532011-09-02 17:16:34 -0700484void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700485 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
486 EmitUint8(0xF3);
487 EmitUint8(0x0F);
488 EmitUint8(0x5E);
489 EmitXmmRegisterOperand(dst, src);
490}
491
492
Ian Rogers2c8f6532011-09-02 17:16:34 -0700493void X86Assembler::divss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700494 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
495 EmitUint8(0xF3);
496 EmitUint8(0x0F);
497 EmitUint8(0x5E);
498 EmitOperand(dst, src);
499}
500
501
Aart Bikc7782262017-01-13 16:20:08 -0800502void X86Assembler::addps(XmmRegister dst, XmmRegister src) {
503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
504 EmitUint8(0x0F);
505 EmitUint8(0x58);
506 EmitXmmRegisterOperand(dst, src);
507}
508
509
510void X86Assembler::subps(XmmRegister dst, XmmRegister src) {
511 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
512 EmitUint8(0x0F);
513 EmitUint8(0x5C);
514 EmitXmmRegisterOperand(dst, src);
515}
516
517
518void X86Assembler::mulps(XmmRegister dst, XmmRegister src) {
519 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
520 EmitUint8(0x0F);
521 EmitUint8(0x59);
522 EmitXmmRegisterOperand(dst, src);
523}
524
525
526void X86Assembler::divps(XmmRegister dst, XmmRegister src) {
527 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
528 EmitUint8(0x0F);
529 EmitUint8(0x5E);
530 EmitXmmRegisterOperand(dst, src);
531}
532
533
534void X86Assembler::movapd(XmmRegister dst, XmmRegister src) {
535 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
536 EmitUint8(0x66);
537 EmitUint8(0x0F);
538 EmitUint8(0x28);
539 EmitXmmRegisterOperand(dst, src);
540}
541
542
543void X86Assembler::movapd(XmmRegister dst, const Address& src) {
544 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
545 EmitUint8(0x66);
546 EmitUint8(0x0F);
547 EmitUint8(0x28);
548 EmitOperand(dst, src);
549}
550
551
552void X86Assembler::movupd(XmmRegister dst, const Address& src) {
553 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
554 EmitUint8(0x66);
555 EmitUint8(0x0F);
556 EmitUint8(0x10);
557 EmitOperand(dst, src);
558}
559
560
561void X86Assembler::movapd(const Address& dst, XmmRegister src) {
562 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
563 EmitUint8(0x66);
564 EmitUint8(0x0F);
565 EmitUint8(0x29);
566 EmitOperand(src, dst);
567}
568
569
570void X86Assembler::movupd(const Address& dst, XmmRegister src) {
571 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
572 EmitUint8(0x66);
573 EmitUint8(0x0F);
574 EmitUint8(0x11);
575 EmitOperand(src, dst);
576}
577
578
Ian Rogers2c8f6532011-09-02 17:16:34 -0700579void X86Assembler::flds(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700580 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
581 EmitUint8(0xD9);
582 EmitOperand(0, src);
583}
584
585
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500586void X86Assembler::fsts(const Address& dst) {
587 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
588 EmitUint8(0xD9);
589 EmitOperand(2, dst);
590}
591
592
Ian Rogers2c8f6532011-09-02 17:16:34 -0700593void X86Assembler::fstps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700594 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
595 EmitUint8(0xD9);
596 EmitOperand(3, dst);
597}
598
599
Ian Rogers2c8f6532011-09-02 17:16:34 -0700600void X86Assembler::movsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700601 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
602 EmitUint8(0xF2);
603 EmitUint8(0x0F);
604 EmitUint8(0x10);
605 EmitOperand(dst, src);
606}
607
608
Ian Rogers2c8f6532011-09-02 17:16:34 -0700609void X86Assembler::movsd(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700610 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
611 EmitUint8(0xF2);
612 EmitUint8(0x0F);
613 EmitUint8(0x11);
614 EmitOperand(src, dst);
615}
616
617
Ian Rogers2c8f6532011-09-02 17:16:34 -0700618void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700619 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
620 EmitUint8(0xF2);
621 EmitUint8(0x0F);
622 EmitUint8(0x11);
623 EmitXmmRegisterOperand(src, dst);
624}
625
626
Nicolas Geoffray234d69d2015-03-09 10:28:50 +0000627void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
629 EmitUint8(0x66);
630 EmitUint8(0x0F);
631 EmitUint8(0x16);
632 EmitOperand(dst, src);
633}
634
635
636void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
637 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
638 EmitUint8(0x66);
639 EmitUint8(0x0F);
640 EmitUint8(0x17);
641 EmitOperand(src, dst);
642}
643
644
Ian Rogers2c8f6532011-09-02 17:16:34 -0700645void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700646 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
647 EmitUint8(0xF2);
648 EmitUint8(0x0F);
649 EmitUint8(0x58);
650 EmitXmmRegisterOperand(dst, src);
651}
652
653
Ian Rogers2c8f6532011-09-02 17:16:34 -0700654void X86Assembler::addsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700655 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
656 EmitUint8(0xF2);
657 EmitUint8(0x0F);
658 EmitUint8(0x58);
659 EmitOperand(dst, src);
660}
661
662
Ian Rogers2c8f6532011-09-02 17:16:34 -0700663void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700664 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
665 EmitUint8(0xF2);
666 EmitUint8(0x0F);
667 EmitUint8(0x5C);
668 EmitXmmRegisterOperand(dst, src);
669}
670
671
Ian Rogers2c8f6532011-09-02 17:16:34 -0700672void X86Assembler::subsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700673 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
674 EmitUint8(0xF2);
675 EmitUint8(0x0F);
676 EmitUint8(0x5C);
677 EmitOperand(dst, src);
678}
679
680
Ian Rogers2c8f6532011-09-02 17:16:34 -0700681void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700682 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
683 EmitUint8(0xF2);
684 EmitUint8(0x0F);
685 EmitUint8(0x59);
686 EmitXmmRegisterOperand(dst, src);
687}
688
689
Ian Rogers2c8f6532011-09-02 17:16:34 -0700690void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700691 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
692 EmitUint8(0xF2);
693 EmitUint8(0x0F);
694 EmitUint8(0x59);
695 EmitOperand(dst, src);
696}
697
698
Ian Rogers2c8f6532011-09-02 17:16:34 -0700699void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700700 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
701 EmitUint8(0xF2);
702 EmitUint8(0x0F);
703 EmitUint8(0x5E);
704 EmitXmmRegisterOperand(dst, src);
705}
706
707
Ian Rogers2c8f6532011-09-02 17:16:34 -0700708void X86Assembler::divsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700709 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
710 EmitUint8(0xF2);
711 EmitUint8(0x0F);
712 EmitUint8(0x5E);
713 EmitOperand(dst, src);
714}
715
716
Aart Bikc7782262017-01-13 16:20:08 -0800717void X86Assembler::addpd(XmmRegister dst, XmmRegister src) {
718 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
719 EmitUint8(0x66);
720 EmitUint8(0x0F);
721 EmitUint8(0x58);
722 EmitXmmRegisterOperand(dst, src);
723}
724
725
726void X86Assembler::subpd(XmmRegister dst, XmmRegister src) {
727 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
728 EmitUint8(0x66);
729 EmitUint8(0x0F);
730 EmitUint8(0x5C);
731 EmitXmmRegisterOperand(dst, src);
732}
733
734
735void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) {
736 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
737 EmitUint8(0x66);
738 EmitUint8(0x0F);
739 EmitUint8(0x59);
740 EmitXmmRegisterOperand(dst, src);
741}
742
743
744void X86Assembler::divpd(XmmRegister dst, XmmRegister src) {
745 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
746 EmitUint8(0x66);
747 EmitUint8(0x0F);
748 EmitUint8(0x5E);
749 EmitXmmRegisterOperand(dst, src);
750}
751
752
Aart Bik68555e92017-02-13 14:28:45 -0800753void X86Assembler::movdqa(XmmRegister dst, XmmRegister src) {
754 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
755 EmitUint8(0x66);
756 EmitUint8(0x0F);
757 EmitUint8(0x6F);
758 EmitXmmRegisterOperand(dst, src);
759}
760
761
762void X86Assembler::movdqa(XmmRegister dst, const Address& src) {
763 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
764 EmitUint8(0x66);
765 EmitUint8(0x0F);
766 EmitUint8(0x6F);
767 EmitOperand(dst, src);
768}
769
770
771void X86Assembler::movdqu(XmmRegister dst, const Address& src) {
772 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
773 EmitUint8(0xF3);
774 EmitUint8(0x0F);
775 EmitUint8(0x6F);
776 EmitOperand(dst, src);
777}
778
779
780void X86Assembler::movdqa(const Address& dst, XmmRegister src) {
781 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
782 EmitUint8(0x66);
783 EmitUint8(0x0F);
784 EmitUint8(0x7F);
785 EmitOperand(src, dst);
786}
787
788
789void X86Assembler::movdqu(const Address& dst, XmmRegister src) {
790 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
791 EmitUint8(0xF3);
792 EmitUint8(0x0F);
793 EmitUint8(0x7F);
794 EmitOperand(src, dst);
795}
796
797
Aart Bike69d7a92017-02-17 11:48:23 -0800798void X86Assembler::paddb(XmmRegister dst, XmmRegister src) {
799 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
800 EmitUint8(0x66);
801 EmitUint8(0x0F);
802 EmitUint8(0xFC);
803 EmitXmmRegisterOperand(dst, src);
804}
805
806
807void X86Assembler::psubb(XmmRegister dst, XmmRegister src) {
808 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
809 EmitUint8(0x66);
810 EmitUint8(0x0F);
811 EmitUint8(0xF8);
812 EmitXmmRegisterOperand(dst, src);
813}
814
815
816void X86Assembler::paddw(XmmRegister dst, XmmRegister src) {
817 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
818 EmitUint8(0x66);
819 EmitUint8(0x0F);
820 EmitUint8(0xFD);
821 EmitXmmRegisterOperand(dst, src);
822}
823
824
825void X86Assembler::psubw(XmmRegister dst, XmmRegister src) {
826 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
827 EmitUint8(0x66);
828 EmitUint8(0x0F);
829 EmitUint8(0xF9);
830 EmitXmmRegisterOperand(dst, src);
831}
832
833
834void X86Assembler::pmullw(XmmRegister dst, XmmRegister src) {
835 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
836 EmitUint8(0x66);
837 EmitUint8(0x0F);
838 EmitUint8(0xD5);
839 EmitXmmRegisterOperand(dst, src);
840}
841
842
Aart Bik68555e92017-02-13 14:28:45 -0800843void X86Assembler::paddd(XmmRegister dst, XmmRegister src) {
844 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
845 EmitUint8(0x66);
846 EmitUint8(0x0F);
847 EmitUint8(0xFE);
848 EmitXmmRegisterOperand(dst, src);
849}
850
851
852void X86Assembler::psubd(XmmRegister dst, XmmRegister src) {
853 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
854 EmitUint8(0x66);
855 EmitUint8(0x0F);
856 EmitUint8(0xFA);
857 EmitXmmRegisterOperand(dst, src);
858}
859
860
861void X86Assembler::pmulld(XmmRegister dst, XmmRegister src) {
862 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
863 EmitUint8(0x66);
864 EmitUint8(0x0F);
865 EmitUint8(0x38);
866 EmitUint8(0x40);
867 EmitXmmRegisterOperand(dst, src);
868}
869
870
Aart Bike69d7a92017-02-17 11:48:23 -0800871void X86Assembler::paddq(XmmRegister dst, XmmRegister src) {
872 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
873 EmitUint8(0x66);
874 EmitUint8(0x0F);
875 EmitUint8(0xD4);
876 EmitXmmRegisterOperand(dst, src);
877}
878
879
880void X86Assembler::psubq(XmmRegister dst, XmmRegister src) {
881 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
882 EmitUint8(0x66);
883 EmitUint8(0x0F);
884 EmitUint8(0xFB);
885 EmitXmmRegisterOperand(dst, src);
886}
887
888
Ian Rogers2c8f6532011-09-02 17:16:34 -0700889void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700890 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
891 EmitUint8(0xF3);
892 EmitUint8(0x0F);
893 EmitUint8(0x2A);
894 EmitOperand(dst, Operand(src));
895}
896
897
Ian Rogers2c8f6532011-09-02 17:16:34 -0700898void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700899 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
900 EmitUint8(0xF2);
901 EmitUint8(0x0F);
902 EmitUint8(0x2A);
903 EmitOperand(dst, Operand(src));
904}
905
906
Ian Rogers2c8f6532011-09-02 17:16:34 -0700907void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700908 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
909 EmitUint8(0xF3);
910 EmitUint8(0x0F);
911 EmitUint8(0x2D);
912 EmitXmmRegisterOperand(dst, src);
913}
914
915
Ian Rogers2c8f6532011-09-02 17:16:34 -0700916void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700917 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
918 EmitUint8(0xF3);
919 EmitUint8(0x0F);
920 EmitUint8(0x5A);
921 EmitXmmRegisterOperand(dst, src);
922}
923
924
Ian Rogers2c8f6532011-09-02 17:16:34 -0700925void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700926 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
927 EmitUint8(0xF2);
928 EmitUint8(0x0F);
929 EmitUint8(0x2D);
930 EmitXmmRegisterOperand(dst, src);
931}
932
933
Ian Rogers2c8f6532011-09-02 17:16:34 -0700934void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700935 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
936 EmitUint8(0xF3);
937 EmitUint8(0x0F);
938 EmitUint8(0x2C);
939 EmitXmmRegisterOperand(dst, src);
940}
941
942
Ian Rogers2c8f6532011-09-02 17:16:34 -0700943void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700944 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
945 EmitUint8(0xF2);
946 EmitUint8(0x0F);
947 EmitUint8(0x2C);
948 EmitXmmRegisterOperand(dst, src);
949}
950
951
Ian Rogers2c8f6532011-09-02 17:16:34 -0700952void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700953 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
954 EmitUint8(0xF2);
955 EmitUint8(0x0F);
956 EmitUint8(0x5A);
957 EmitXmmRegisterOperand(dst, src);
958}
959
960
Aart Bik3ae3b592017-02-24 14:09:15 -0800961void X86Assembler::cvtdq2ps(XmmRegister dst, XmmRegister src) {
962 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
963 EmitUint8(0x0F);
964 EmitUint8(0x5B);
965 EmitXmmRegisterOperand(dst, src);
966}
967
968
Ian Rogers2c8f6532011-09-02 17:16:34 -0700969void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700970 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
971 EmitUint8(0xF3);
972 EmitUint8(0x0F);
973 EmitUint8(0xE6);
974 EmitXmmRegisterOperand(dst, src);
975}
976
977
Ian Rogers2c8f6532011-09-02 17:16:34 -0700978void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700979 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
980 EmitUint8(0x0F);
981 EmitUint8(0x2F);
982 EmitXmmRegisterOperand(a, b);
983}
984
985
Aart Bik18ba1212016-08-01 14:11:20 -0700986void X86Assembler::comiss(XmmRegister a, const Address& b) {
987 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
988 EmitUint8(0x0F);
989 EmitUint8(0x2F);
990 EmitOperand(a, b);
991}
992
993
Ian Rogers2c8f6532011-09-02 17:16:34 -0700994void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700995 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
996 EmitUint8(0x66);
997 EmitUint8(0x0F);
998 EmitUint8(0x2F);
999 EmitXmmRegisterOperand(a, b);
1000}
1001
1002
Aart Bik18ba1212016-08-01 14:11:20 -07001003void X86Assembler::comisd(XmmRegister a, const Address& b) {
1004 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1005 EmitUint8(0x66);
1006 EmitUint8(0x0F);
1007 EmitUint8(0x2F);
1008 EmitOperand(a, b);
1009}
1010
1011
Calin Juravleddb7df22014-11-25 20:56:51 +00001012void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
1013 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1014 EmitUint8(0x0F);
1015 EmitUint8(0x2E);
1016 EmitXmmRegisterOperand(a, b);
1017}
1018
1019
Mark Mendell9f51f262015-10-30 09:21:37 -04001020void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
1021 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1022 EmitUint8(0x0F);
1023 EmitUint8(0x2E);
1024 EmitOperand(a, b);
1025}
1026
1027
Calin Juravleddb7df22014-11-25 20:56:51 +00001028void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
1029 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1030 EmitUint8(0x66);
1031 EmitUint8(0x0F);
1032 EmitUint8(0x2E);
1033 EmitXmmRegisterOperand(a, b);
1034}
1035
1036
Mark Mendell9f51f262015-10-30 09:21:37 -04001037void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
1038 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1039 EmitUint8(0x66);
1040 EmitUint8(0x0F);
1041 EmitUint8(0x2E);
1042 EmitOperand(a, b);
1043}
1044
1045
Mark Mendellfb8d2792015-03-31 22:16:59 -04001046void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1047 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1048 EmitUint8(0x66);
1049 EmitUint8(0x0F);
1050 EmitUint8(0x3A);
1051 EmitUint8(0x0B);
1052 EmitXmmRegisterOperand(dst, src);
1053 EmitUint8(imm.value());
1054}
1055
1056
1057void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1058 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1059 EmitUint8(0x66);
1060 EmitUint8(0x0F);
1061 EmitUint8(0x3A);
1062 EmitUint8(0x0A);
1063 EmitXmmRegisterOperand(dst, src);
1064 EmitUint8(imm.value());
1065}
1066
1067
Ian Rogers2c8f6532011-09-02 17:16:34 -07001068void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1070 EmitUint8(0xF2);
1071 EmitUint8(0x0F);
1072 EmitUint8(0x51);
1073 EmitXmmRegisterOperand(dst, src);
1074}
1075
1076
Ian Rogers2c8f6532011-09-02 17:16:34 -07001077void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001078 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1079 EmitUint8(0xF3);
1080 EmitUint8(0x0F);
1081 EmitUint8(0x51);
1082 EmitXmmRegisterOperand(dst, src);
1083}
1084
1085
Ian Rogers2c8f6532011-09-02 17:16:34 -07001086void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001087 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1088 EmitUint8(0x66);
1089 EmitUint8(0x0F);
1090 EmitUint8(0x57);
1091 EmitOperand(dst, src);
1092}
1093
1094
Ian Rogers2c8f6532011-09-02 17:16:34 -07001095void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001096 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1097 EmitUint8(0x66);
1098 EmitUint8(0x0F);
1099 EmitUint8(0x57);
1100 EmitXmmRegisterOperand(dst, src);
1101}
1102
1103
Aart Bik68555e92017-02-13 14:28:45 -08001104void X86Assembler::xorps(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001105 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1106 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001107 EmitUint8(0x57);
1108 EmitOperand(dst, src);
1109}
1110
1111
1112void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
1113 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1114 EmitUint8(0x0F);
1115 EmitUint8(0x57);
1116 EmitXmmRegisterOperand(dst, src);
1117}
1118
1119
1120void X86Assembler::pxor(XmmRegister dst, XmmRegister src) {
1121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1122 EmitUint8(0x66);
1123 EmitUint8(0x0F);
1124 EmitUint8(0xEF);
Mark Mendell09ed1a32015-03-25 08:30:06 -04001125 EmitXmmRegisterOperand(dst, src);
1126}
1127
1128
1129void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
1130 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1131 EmitUint8(0x66);
1132 EmitUint8(0x0F);
1133 EmitUint8(0x54);
1134 EmitXmmRegisterOperand(dst, src);
1135}
1136
1137
Aart Bik68555e92017-02-13 14:28:45 -08001138void X86Assembler::andpd(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001139 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1140 EmitUint8(0x66);
1141 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001142 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001143 EmitOperand(dst, src);
1144}
1145
1146
Aart Bik68555e92017-02-13 14:28:45 -08001147void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001148 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1149 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001150 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001151 EmitXmmRegisterOperand(dst, src);
1152}
1153
1154
Mark Mendell09ed1a32015-03-25 08:30:06 -04001155void X86Assembler::andps(XmmRegister dst, const Address& src) {
1156 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1157 EmitUint8(0x0F);
1158 EmitUint8(0x54);
1159 EmitOperand(dst, src);
1160}
1161
1162
Aart Bik68555e92017-02-13 14:28:45 -08001163void X86Assembler::pand(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001164 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1165 EmitUint8(0x66);
1166 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001167 EmitUint8(0xDB);
1168 EmitXmmRegisterOperand(dst, src);
1169}
1170
1171
Aart Bik21c580b2017-03-13 11:52:07 -07001172void X86Assembler::andnpd(XmmRegister dst, XmmRegister src) {
1173 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1174 EmitUint8(0x66);
1175 EmitUint8(0x0F);
1176 EmitUint8(0x55);
1177 EmitXmmRegisterOperand(dst, src);
1178}
1179
1180
1181void X86Assembler::andnps(XmmRegister dst, XmmRegister src) {
1182 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1183 EmitUint8(0x0F);
1184 EmitUint8(0x55);
1185 EmitXmmRegisterOperand(dst, src);
1186}
1187
1188
1189void X86Assembler::pandn(XmmRegister dst, XmmRegister src) {
1190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1191 EmitUint8(0x66);
1192 EmitUint8(0x0F);
1193 EmitUint8(0xDF);
1194 EmitXmmRegisterOperand(dst, src);
1195}
1196
1197
Aart Bik68555e92017-02-13 14:28:45 -08001198void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
1199 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1200 EmitUint8(0x66);
1201 EmitUint8(0x0F);
1202 EmitUint8(0x56);
1203 EmitXmmRegisterOperand(dst, src);
1204}
1205
1206
1207void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
1208 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1209 EmitUint8(0x0F);
1210 EmitUint8(0x56);
1211 EmitXmmRegisterOperand(dst, src);
1212}
1213
1214
1215void X86Assembler::por(XmmRegister dst, XmmRegister src) {
1216 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1217 EmitUint8(0x66);
1218 EmitUint8(0x0F);
1219 EmitUint8(0xEB);
1220 EmitXmmRegisterOperand(dst, src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001221}
1222
1223
Aart Bik67d3fd72017-03-31 15:11:53 -07001224void X86Assembler::pavgb(XmmRegister dst, XmmRegister src) {
1225 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1226 EmitUint8(0x66);
1227 EmitUint8(0x0F);
1228 EmitUint8(0xE0);
1229 EmitXmmRegisterOperand(dst, src);
1230}
1231
1232
1233void X86Assembler::pavgw(XmmRegister dst, XmmRegister src) {
1234 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1235 EmitUint8(0x66);
1236 EmitUint8(0x0F);
1237 EmitUint8(0xE3);
1238 EmitXmmRegisterOperand(dst, src);
1239}
1240
Aart Bik6005a872017-07-24 13:33:39 -07001241
1242void X86Assembler::psadbw(XmmRegister dst, XmmRegister src) {
1243 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1244 EmitUint8(0x66);
1245 EmitUint8(0x0F);
1246 EmitUint8(0xF6);
1247 EmitXmmRegisterOperand(dst, src);
1248}
1249
1250
1251void X86Assembler::pmaddwd(XmmRegister dst, XmmRegister src) {
1252 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1253 EmitUint8(0x66);
1254 EmitUint8(0x0F);
1255 EmitUint8(0xF5);
1256 EmitXmmRegisterOperand(dst, src);
1257}
1258
1259
1260void X86Assembler::phaddw(XmmRegister dst, XmmRegister src) {
1261 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1262 EmitUint8(0x66);
1263 EmitUint8(0x0F);
1264 EmitUint8(0x38);
1265 EmitUint8(0x01);
1266 EmitXmmRegisterOperand(dst, src);
1267}
1268
1269
1270void X86Assembler::phaddd(XmmRegister dst, XmmRegister src) {
1271 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1272 EmitUint8(0x66);
1273 EmitUint8(0x0F);
1274 EmitUint8(0x38);
1275 EmitUint8(0x02);
1276 EmitXmmRegisterOperand(dst, src);
1277}
1278
1279
1280void X86Assembler::haddps(XmmRegister dst, XmmRegister src) {
1281 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1282 EmitUint8(0xF2);
1283 EmitUint8(0x0F);
1284 EmitUint8(0x7C);
1285 EmitXmmRegisterOperand(dst, src);
1286}
1287
1288
1289void X86Assembler::haddpd(XmmRegister dst, XmmRegister src) {
1290 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1291 EmitUint8(0x66);
1292 EmitUint8(0x0F);
1293 EmitUint8(0x7C);
1294 EmitXmmRegisterOperand(dst, src);
1295}
1296
1297
1298void X86Assembler::phsubw(XmmRegister dst, XmmRegister src) {
1299 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1300 EmitUint8(0x66);
1301 EmitUint8(0x0F);
1302 EmitUint8(0x38);
1303 EmitUint8(0x05);
1304 EmitXmmRegisterOperand(dst, src);
1305}
1306
1307
1308void X86Assembler::phsubd(XmmRegister dst, XmmRegister src) {
1309 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1310 EmitUint8(0x66);
1311 EmitUint8(0x0F);
1312 EmitUint8(0x38);
1313 EmitUint8(0x06);
1314 EmitXmmRegisterOperand(dst, src);
1315}
1316
1317
1318void X86Assembler::hsubps(XmmRegister dst, XmmRegister src) {
1319 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1320 EmitUint8(0xF2);
1321 EmitUint8(0x0F);
1322 EmitUint8(0x7D);
1323 EmitXmmRegisterOperand(dst, src);
1324}
1325
1326
1327void X86Assembler::hsubpd(XmmRegister dst, XmmRegister src) {
1328 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1329 EmitUint8(0x66);
1330 EmitUint8(0x0F);
1331 EmitUint8(0x7D);
1332 EmitXmmRegisterOperand(dst, src);
1333}
1334
1335
Aart Bikc8e93c72017-05-10 10:49:22 -07001336void X86Assembler::pminsb(XmmRegister dst, XmmRegister src) {
1337 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1338 EmitUint8(0x66);
1339 EmitUint8(0x0F);
1340 EmitUint8(0x38);
1341 EmitUint8(0x38);
1342 EmitXmmRegisterOperand(dst, src);
1343}
1344
1345void X86Assembler::pmaxsb(XmmRegister dst, XmmRegister src) {
1346 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1347 EmitUint8(0x66);
1348 EmitUint8(0x0F);
1349 EmitUint8(0x38);
1350 EmitUint8(0x3C);
1351 EmitXmmRegisterOperand(dst, src);
1352}
1353
1354void X86Assembler::pminsw(XmmRegister dst, XmmRegister src) {
1355 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1356 EmitUint8(0x66);
1357 EmitUint8(0x0F);
1358 EmitUint8(0xEA);
1359 EmitXmmRegisterOperand(dst, src);
1360}
1361
1362void X86Assembler::pmaxsw(XmmRegister dst, XmmRegister src) {
1363 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1364 EmitUint8(0x66);
1365 EmitUint8(0x0F);
1366 EmitUint8(0xEE);
1367 EmitXmmRegisterOperand(dst, src);
1368}
1369
1370void X86Assembler::pminsd(XmmRegister dst, XmmRegister src) {
1371 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1372 EmitUint8(0x66);
1373 EmitUint8(0x0F);
1374 EmitUint8(0x38);
1375 EmitUint8(0x39);
1376 EmitXmmRegisterOperand(dst, src);
1377}
1378
1379void X86Assembler::pmaxsd(XmmRegister dst, XmmRegister src) {
1380 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1381 EmitUint8(0x66);
1382 EmitUint8(0x0F);
1383 EmitUint8(0x38);
1384 EmitUint8(0x3D);
1385 EmitXmmRegisterOperand(dst, src);
1386}
1387
1388void X86Assembler::pminub(XmmRegister dst, XmmRegister src) {
1389 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1390 EmitUint8(0x66);
1391 EmitUint8(0x0F);
1392 EmitUint8(0xDA);
1393 EmitXmmRegisterOperand(dst, src);
1394}
1395
1396void X86Assembler::pmaxub(XmmRegister dst, XmmRegister src) {
1397 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1398 EmitUint8(0x66);
1399 EmitUint8(0x0F);
1400 EmitUint8(0xDE);
1401 EmitXmmRegisterOperand(dst, src);
1402}
1403
1404void X86Assembler::pminuw(XmmRegister dst, XmmRegister src) {
1405 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1406 EmitUint8(0x66);
1407 EmitUint8(0x0F);
1408 EmitUint8(0x38);
1409 EmitUint8(0x3A);
1410 EmitXmmRegisterOperand(dst, src);
1411}
1412
1413void X86Assembler::pmaxuw(XmmRegister dst, XmmRegister src) {
1414 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1415 EmitUint8(0x66);
1416 EmitUint8(0x0F);
1417 EmitUint8(0x38);
1418 EmitUint8(0x3E);
1419 EmitXmmRegisterOperand(dst, src);
1420}
1421
1422void X86Assembler::pminud(XmmRegister dst, XmmRegister src) {
1423 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1424 EmitUint8(0x66);
1425 EmitUint8(0x0F);
1426 EmitUint8(0x38);
1427 EmitUint8(0x3B);
1428 EmitXmmRegisterOperand(dst, src);
1429}
1430
1431void X86Assembler::pmaxud(XmmRegister dst, XmmRegister src) {
1432 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1433 EmitUint8(0x66);
1434 EmitUint8(0x0F);
1435 EmitUint8(0x38);
1436 EmitUint8(0x3F);
1437 EmitXmmRegisterOperand(dst, src);
1438}
1439
1440void X86Assembler::minps(XmmRegister dst, XmmRegister src) {
1441 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1442 EmitUint8(0x0F);
1443 EmitUint8(0x5D);
1444 EmitXmmRegisterOperand(dst, src);
1445}
1446
1447void X86Assembler::maxps(XmmRegister dst, XmmRegister src) {
1448 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1449 EmitUint8(0x0F);
1450 EmitUint8(0x5F);
1451 EmitXmmRegisterOperand(dst, src);
1452}
1453
1454void X86Assembler::minpd(XmmRegister dst, XmmRegister src) {
1455 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1456 EmitUint8(0x66);
1457 EmitUint8(0x0F);
1458 EmitUint8(0x5D);
1459 EmitXmmRegisterOperand(dst, src);
1460}
1461
1462void X86Assembler::maxpd(XmmRegister dst, XmmRegister src) {
1463 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1464 EmitUint8(0x66);
1465 EmitUint8(0x0F);
1466 EmitUint8(0x5F);
1467 EmitXmmRegisterOperand(dst, src);
1468}
Aart Bik67d3fd72017-03-31 15:11:53 -07001469
Aart Bik4b455332017-03-15 11:19:35 -07001470void X86Assembler::pcmpeqb(XmmRegister dst, XmmRegister src) {
1471 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1472 EmitUint8(0x66);
1473 EmitUint8(0x0F);
1474 EmitUint8(0x74);
1475 EmitXmmRegisterOperand(dst, src);
1476}
1477
1478
1479void X86Assembler::pcmpeqw(XmmRegister dst, XmmRegister src) {
1480 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1481 EmitUint8(0x66);
1482 EmitUint8(0x0F);
1483 EmitUint8(0x75);
1484 EmitXmmRegisterOperand(dst, src);
1485}
1486
1487
1488void X86Assembler::pcmpeqd(XmmRegister dst, XmmRegister src) {
1489 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1490 EmitUint8(0x66);
1491 EmitUint8(0x0F);
1492 EmitUint8(0x76);
1493 EmitXmmRegisterOperand(dst, src);
1494}
1495
1496
1497void X86Assembler::pcmpeqq(XmmRegister dst, XmmRegister src) {
1498 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1499 EmitUint8(0x66);
1500 EmitUint8(0x0F);
1501 EmitUint8(0x38);
1502 EmitUint8(0x29);
1503 EmitXmmRegisterOperand(dst, src);
1504}
1505
1506
Aart Bik8939c642017-04-03 14:09:01 -07001507void X86Assembler::pcmpgtb(XmmRegister dst, XmmRegister src) {
1508 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1509 EmitUint8(0x66);
1510 EmitUint8(0x0F);
1511 EmitUint8(0x64);
1512 EmitXmmRegisterOperand(dst, src);
1513}
1514
1515
1516void X86Assembler::pcmpgtw(XmmRegister dst, XmmRegister src) {
1517 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1518 EmitUint8(0x66);
1519 EmitUint8(0x0F);
1520 EmitUint8(0x65);
1521 EmitXmmRegisterOperand(dst, src);
1522}
1523
1524
1525void X86Assembler::pcmpgtd(XmmRegister dst, XmmRegister src) {
1526 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1527 EmitUint8(0x66);
1528 EmitUint8(0x0F);
1529 EmitUint8(0x66);
1530 EmitXmmRegisterOperand(dst, src);
1531}
1532
1533
1534void X86Assembler::pcmpgtq(XmmRegister dst, XmmRegister src) {
1535 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1536 EmitUint8(0x66);
1537 EmitUint8(0x0F);
1538 EmitUint8(0x38);
1539 EmitUint8(0x37);
1540 EmitXmmRegisterOperand(dst, src);
1541}
1542
1543
Aart Bik12e06ed2017-01-31 16:11:24 -08001544void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1545 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1546 EmitUint8(0x66);
1547 EmitUint8(0x0F);
1548 EmitUint8(0xC6);
1549 EmitXmmRegisterOperand(dst, src);
1550 EmitUint8(imm.value());
1551}
1552
1553
1554void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1555 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1556 EmitUint8(0x0F);
1557 EmitUint8(0xC6);
1558 EmitXmmRegisterOperand(dst, src);
1559 EmitUint8(imm.value());
1560}
1561
1562
Aart Bik68555e92017-02-13 14:28:45 -08001563void X86Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1564 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1565 EmitUint8(0x66);
1566 EmitUint8(0x0F);
1567 EmitUint8(0x70);
1568 EmitXmmRegisterOperand(dst, src);
1569 EmitUint8(imm.value());
1570}
1571
1572
Aart Bike69d7a92017-02-17 11:48:23 -08001573void X86Assembler::punpcklbw(XmmRegister dst, XmmRegister src) {
1574 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1575 EmitUint8(0x66);
1576 EmitUint8(0x0F);
1577 EmitUint8(0x60);
1578 EmitXmmRegisterOperand(dst, src);
1579}
1580
1581
1582void X86Assembler::punpcklwd(XmmRegister dst, XmmRegister src) {
1583 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1584 EmitUint8(0x66);
1585 EmitUint8(0x0F);
1586 EmitUint8(0x61);
1587 EmitXmmRegisterOperand(dst, src);
1588}
1589
1590
1591void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
1592 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1593 EmitUint8(0x66);
1594 EmitUint8(0x0F);
1595 EmitUint8(0x62);
1596 EmitXmmRegisterOperand(dst, src);
1597}
1598
1599
1600void X86Assembler::punpcklqdq(XmmRegister dst, XmmRegister src) {
1601 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1602 EmitUint8(0x66);
1603 EmitUint8(0x0F);
1604 EmitUint8(0x6C);
1605 EmitXmmRegisterOperand(dst, src);
1606}
1607
1608
Aart Bik3332db82017-08-11 15:10:30 -07001609void X86Assembler::punpckhbw(XmmRegister dst, XmmRegister src) {
1610 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1611 EmitUint8(0x66);
1612 EmitUint8(0x0F);
1613 EmitUint8(0x68);
1614 EmitXmmRegisterOperand(dst, src);
1615}
1616
1617
1618void X86Assembler::punpckhwd(XmmRegister dst, XmmRegister src) {
1619 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1620 EmitUint8(0x66);
1621 EmitUint8(0x0F);
1622 EmitUint8(0x69);
1623 EmitXmmRegisterOperand(dst, src);
1624}
1625
1626
1627void X86Assembler::punpckhdq(XmmRegister dst, XmmRegister src) {
1628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1629 EmitUint8(0x66);
1630 EmitUint8(0x0F);
1631 EmitUint8(0x6A);
1632 EmitXmmRegisterOperand(dst, src);
1633}
1634
1635
1636void X86Assembler::punpckhqdq(XmmRegister dst, XmmRegister src) {
1637 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1638 EmitUint8(0x66);
1639 EmitUint8(0x0F);
1640 EmitUint8(0x6D);
1641 EmitXmmRegisterOperand(dst, src);
1642}
1643
1644
Aart Bike69d7a92017-02-17 11:48:23 -08001645void X86Assembler::psllw(XmmRegister reg, const Immediate& shift_count) {
1646 DCHECK(shift_count.is_uint8());
1647 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1648 EmitUint8(0x66);
1649 EmitUint8(0x0F);
1650 EmitUint8(0x71);
1651 EmitXmmRegisterOperand(6, reg);
1652 EmitUint8(shift_count.value());
1653}
1654
1655
1656void X86Assembler::pslld(XmmRegister reg, const Immediate& shift_count) {
1657 DCHECK(shift_count.is_uint8());
1658 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1659 EmitUint8(0x66);
1660 EmitUint8(0x0F);
1661 EmitUint8(0x72);
1662 EmitXmmRegisterOperand(6, reg);
1663 EmitUint8(shift_count.value());
1664}
1665
1666
1667void X86Assembler::psllq(XmmRegister reg, const Immediate& shift_count) {
1668 DCHECK(shift_count.is_uint8());
1669 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1670 EmitUint8(0x66);
1671 EmitUint8(0x0F);
1672 EmitUint8(0x73);
1673 EmitXmmRegisterOperand(6, reg);
1674 EmitUint8(shift_count.value());
1675}
1676
1677
1678void X86Assembler::psraw(XmmRegister reg, const Immediate& shift_count) {
1679 DCHECK(shift_count.is_uint8());
1680 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1681 EmitUint8(0x66);
1682 EmitUint8(0x0F);
1683 EmitUint8(0x71);
1684 EmitXmmRegisterOperand(4, reg);
1685 EmitUint8(shift_count.value());
1686}
1687
1688
1689void X86Assembler::psrad(XmmRegister reg, const Immediate& shift_count) {
1690 DCHECK(shift_count.is_uint8());
1691 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1692 EmitUint8(0x66);
1693 EmitUint8(0x0F);
1694 EmitUint8(0x72);
1695 EmitXmmRegisterOperand(4, reg);
1696 EmitUint8(shift_count.value());
1697}
1698
1699
1700void X86Assembler::psrlw(XmmRegister reg, const Immediate& shift_count) {
1701 DCHECK(shift_count.is_uint8());
1702 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1703 EmitUint8(0x66);
1704 EmitUint8(0x0F);
1705 EmitUint8(0x71);
1706 EmitXmmRegisterOperand(2, reg);
1707 EmitUint8(shift_count.value());
1708}
1709
1710
1711void X86Assembler::psrld(XmmRegister reg, const Immediate& shift_count) {
1712 DCHECK(shift_count.is_uint8());
1713 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1714 EmitUint8(0x66);
1715 EmitUint8(0x0F);
1716 EmitUint8(0x72);
1717 EmitXmmRegisterOperand(2, reg);
1718 EmitUint8(shift_count.value());
1719}
1720
1721
1722void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) {
1723 DCHECK(shift_count.is_uint8());
1724 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1725 EmitUint8(0x66);
1726 EmitUint8(0x0F);
1727 EmitUint8(0x73);
1728 EmitXmmRegisterOperand(2, reg);
1729 EmitUint8(shift_count.value());
1730}
1731
1732
1733void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) {
1734 DCHECK(shift_count.is_uint8());
1735 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1736 EmitUint8(0x66);
1737 EmitUint8(0x0F);
1738 EmitUint8(0x73);
1739 EmitXmmRegisterOperand(3, reg);
1740 EmitUint8(shift_count.value());
1741}
1742
1743
Ian Rogers2c8f6532011-09-02 17:16:34 -07001744void X86Assembler::fldl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001745 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1746 EmitUint8(0xDD);
1747 EmitOperand(0, src);
1748}
1749
1750
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001751void X86Assembler::fstl(const Address& dst) {
1752 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1753 EmitUint8(0xDD);
1754 EmitOperand(2, dst);
1755}
1756
1757
Ian Rogers2c8f6532011-09-02 17:16:34 -07001758void X86Assembler::fstpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001759 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1760 EmitUint8(0xDD);
1761 EmitOperand(3, dst);
1762}
1763
1764
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001765void X86Assembler::fstsw() {
1766 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1767 EmitUint8(0x9B);
1768 EmitUint8(0xDF);
1769 EmitUint8(0xE0);
1770}
1771
1772
Ian Rogers2c8f6532011-09-02 17:16:34 -07001773void X86Assembler::fnstcw(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001774 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1775 EmitUint8(0xD9);
1776 EmitOperand(7, dst);
1777}
1778
1779
Ian Rogers2c8f6532011-09-02 17:16:34 -07001780void X86Assembler::fldcw(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001781 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1782 EmitUint8(0xD9);
1783 EmitOperand(5, src);
1784}
1785
1786
Ian Rogers2c8f6532011-09-02 17:16:34 -07001787void X86Assembler::fistpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001788 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1789 EmitUint8(0xDF);
1790 EmitOperand(7, dst);
1791}
1792
1793
Ian Rogers2c8f6532011-09-02 17:16:34 -07001794void X86Assembler::fistps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001795 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1796 EmitUint8(0xDB);
1797 EmitOperand(3, dst);
1798}
1799
1800
Ian Rogers2c8f6532011-09-02 17:16:34 -07001801void X86Assembler::fildl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001802 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1803 EmitUint8(0xDF);
1804 EmitOperand(5, src);
1805}
1806
1807
Roland Levillain0a186012015-04-13 17:00:20 +01001808void X86Assembler::filds(const Address& src) {
1809 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1810 EmitUint8(0xDB);
1811 EmitOperand(0, src);
1812}
1813
1814
Ian Rogers2c8f6532011-09-02 17:16:34 -07001815void X86Assembler::fincstp() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001816 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1817 EmitUint8(0xD9);
1818 EmitUint8(0xF7);
1819}
1820
1821
Ian Rogers2c8f6532011-09-02 17:16:34 -07001822void X86Assembler::ffree(const Immediate& index) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001823 CHECK_LT(index.value(), 7);
1824 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1825 EmitUint8(0xDD);
1826 EmitUint8(0xC0 + index.value());
1827}
1828
1829
Ian Rogers2c8f6532011-09-02 17:16:34 -07001830void X86Assembler::fsin() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001831 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1832 EmitUint8(0xD9);
1833 EmitUint8(0xFE);
1834}
1835
1836
Ian Rogers2c8f6532011-09-02 17:16:34 -07001837void X86Assembler::fcos() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001838 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1839 EmitUint8(0xD9);
1840 EmitUint8(0xFF);
1841}
1842
1843
Ian Rogers2c8f6532011-09-02 17:16:34 -07001844void X86Assembler::fptan() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001845 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1846 EmitUint8(0xD9);
1847 EmitUint8(0xF2);
1848}
1849
1850
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001851void X86Assembler::fucompp() {
1852 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1853 EmitUint8(0xDA);
1854 EmitUint8(0xE9);
1855}
1856
1857
1858void X86Assembler::fprem() {
1859 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1860 EmitUint8(0xD9);
1861 EmitUint8(0xF8);
1862}
1863
1864
Ian Rogers2c8f6532011-09-02 17:16:34 -07001865void X86Assembler::xchgl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001866 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1867 EmitUint8(0x87);
1868 EmitRegisterOperand(dst, src);
1869}
1870
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001871
Ian Rogers7caad772012-03-30 01:07:54 -07001872void X86Assembler::xchgl(Register reg, const Address& address) {
1873 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1874 EmitUint8(0x87);
1875 EmitOperand(reg, address);
1876}
1877
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001878
Serguei Katkov3b625932016-05-06 10:24:17 +06001879void X86Assembler::cmpb(const Address& address, const Immediate& imm) {
1880 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1881 EmitUint8(0x80);
1882 EmitOperand(7, address);
1883 EmitUint8(imm.value() & 0xFF);
1884}
1885
1886
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001887void X86Assembler::cmpw(const Address& address, const Immediate& imm) {
1888 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1889 EmitUint8(0x66);
1890 EmitComplex(7, address, imm);
1891}
1892
1893
Ian Rogers2c8f6532011-09-02 17:16:34 -07001894void X86Assembler::cmpl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001895 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1896 EmitComplex(7, Operand(reg), imm);
1897}
1898
1899
Ian Rogers2c8f6532011-09-02 17:16:34 -07001900void X86Assembler::cmpl(Register reg0, Register reg1) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001901 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1902 EmitUint8(0x3B);
1903 EmitOperand(reg0, Operand(reg1));
1904}
1905
1906
Ian Rogers2c8f6532011-09-02 17:16:34 -07001907void X86Assembler::cmpl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001908 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1909 EmitUint8(0x3B);
1910 EmitOperand(reg, address);
1911}
1912
1913
Ian Rogers2c8f6532011-09-02 17:16:34 -07001914void X86Assembler::addl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001915 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1916 EmitUint8(0x03);
1917 EmitRegisterOperand(dst, src);
1918}
1919
1920
Ian Rogers2c8f6532011-09-02 17:16:34 -07001921void X86Assembler::addl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001922 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1923 EmitUint8(0x03);
1924 EmitOperand(reg, address);
1925}
1926
1927
Ian Rogers2c8f6532011-09-02 17:16:34 -07001928void X86Assembler::cmpl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001929 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1930 EmitUint8(0x39);
1931 EmitOperand(reg, address);
1932}
1933
1934
Ian Rogers2c8f6532011-09-02 17:16:34 -07001935void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001936 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1937 EmitComplex(7, address, imm);
1938}
1939
1940
Ian Rogers2c8f6532011-09-02 17:16:34 -07001941void X86Assembler::testl(Register reg1, Register reg2) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001942 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1943 EmitUint8(0x85);
1944 EmitRegisterOperand(reg1, reg2);
1945}
1946
1947
Nicolas Geoffrayf12feb82014-07-17 18:32:41 +01001948void X86Assembler::testl(Register reg, const Address& address) {
1949 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1950 EmitUint8(0x85);
1951 EmitOperand(reg, address);
1952}
1953
1954
Ian Rogers2c8f6532011-09-02 17:16:34 -07001955void X86Assembler::testl(Register reg, const Immediate& immediate) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001956 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1957 // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
1958 // we only test the byte register to keep the encoding short.
1959 if (immediate.is_uint8() && reg < 4) {
1960 // Use zero-extended 8-bit immediate.
1961 if (reg == EAX) {
1962 EmitUint8(0xA8);
1963 } else {
1964 EmitUint8(0xF6);
1965 EmitUint8(0xC0 + reg);
1966 }
1967 EmitUint8(immediate.value() & 0xFF);
1968 } else if (reg == EAX) {
1969 // Use short form if the destination is EAX.
1970 EmitUint8(0xA9);
1971 EmitImmediate(immediate);
1972 } else {
1973 EmitUint8(0xF7);
1974 EmitOperand(0, Operand(reg));
1975 EmitImmediate(immediate);
1976 }
1977}
1978
1979
Vladimir Marko953437b2016-08-24 08:30:46 +00001980void X86Assembler::testb(const Address& dst, const Immediate& imm) {
1981 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1982 EmitUint8(0xF6);
1983 EmitOperand(EAX, dst);
1984 CHECK(imm.is_int8());
1985 EmitUint8(imm.value() & 0xFF);
1986}
1987
1988
1989void X86Assembler::testl(const Address& dst, const Immediate& imm) {
1990 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1991 EmitUint8(0xF7);
1992 EmitOperand(0, dst);
1993 EmitImmediate(imm);
1994}
1995
1996
Ian Rogers2c8f6532011-09-02 17:16:34 -07001997void X86Assembler::andl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001998 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1999 EmitUint8(0x23);
2000 EmitOperand(dst, Operand(src));
2001}
2002
2003
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002004void X86Assembler::andl(Register reg, const Address& address) {
2005 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2006 EmitUint8(0x23);
2007 EmitOperand(reg, address);
2008}
2009
2010
Ian Rogers2c8f6532011-09-02 17:16:34 -07002011void X86Assembler::andl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002012 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2013 EmitComplex(4, Operand(dst), imm);
2014}
2015
2016
Ian Rogers2c8f6532011-09-02 17:16:34 -07002017void X86Assembler::orl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002018 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2019 EmitUint8(0x0B);
2020 EmitOperand(dst, Operand(src));
2021}
2022
2023
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002024void X86Assembler::orl(Register reg, const Address& address) {
2025 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2026 EmitUint8(0x0B);
2027 EmitOperand(reg, address);
2028}
2029
2030
Ian Rogers2c8f6532011-09-02 17:16:34 -07002031void X86Assembler::orl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002032 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2033 EmitComplex(1, Operand(dst), imm);
2034}
2035
2036
Ian Rogers2c8f6532011-09-02 17:16:34 -07002037void X86Assembler::xorl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002038 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2039 EmitUint8(0x33);
2040 EmitOperand(dst, Operand(src));
2041}
2042
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002043
2044void X86Assembler::xorl(Register reg, const Address& address) {
2045 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2046 EmitUint8(0x33);
2047 EmitOperand(reg, address);
2048}
2049
2050
Nicolas Geoffrayb55f8352014-04-07 15:26:35 +01002051void X86Assembler::xorl(Register dst, const Immediate& imm) {
2052 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2053 EmitComplex(6, Operand(dst), imm);
2054}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002055
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002056
Ian Rogers2c8f6532011-09-02 17:16:34 -07002057void X86Assembler::addl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002058 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2059 EmitComplex(0, Operand(reg), imm);
2060}
2061
2062
Ian Rogers2c8f6532011-09-02 17:16:34 -07002063void X86Assembler::addl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002064 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2065 EmitUint8(0x01);
2066 EmitOperand(reg, address);
2067}
2068
2069
Ian Rogers2c8f6532011-09-02 17:16:34 -07002070void X86Assembler::addl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002071 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2072 EmitComplex(0, address, imm);
2073}
2074
2075
Ian Rogers2c8f6532011-09-02 17:16:34 -07002076void X86Assembler::adcl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002077 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2078 EmitComplex(2, Operand(reg), imm);
2079}
2080
2081
Ian Rogers2c8f6532011-09-02 17:16:34 -07002082void X86Assembler::adcl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002083 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2084 EmitUint8(0x13);
2085 EmitOperand(dst, Operand(src));
2086}
2087
2088
Ian Rogers2c8f6532011-09-02 17:16:34 -07002089void X86Assembler::adcl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002090 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2091 EmitUint8(0x13);
2092 EmitOperand(dst, address);
2093}
2094
2095
Ian Rogers2c8f6532011-09-02 17:16:34 -07002096void X86Assembler::subl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002097 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2098 EmitUint8(0x2B);
2099 EmitOperand(dst, Operand(src));
2100}
2101
2102
Ian Rogers2c8f6532011-09-02 17:16:34 -07002103void X86Assembler::subl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002104 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2105 EmitComplex(5, Operand(reg), imm);
2106}
2107
2108
Ian Rogers2c8f6532011-09-02 17:16:34 -07002109void X86Assembler::subl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002110 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2111 EmitUint8(0x2B);
2112 EmitOperand(reg, address);
2113}
2114
2115
Mark Mendell09ed1a32015-03-25 08:30:06 -04002116void X86Assembler::subl(const Address& address, Register reg) {
2117 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2118 EmitUint8(0x29);
2119 EmitOperand(reg, address);
2120}
2121
2122
Ian Rogers2c8f6532011-09-02 17:16:34 -07002123void X86Assembler::cdq() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002124 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2125 EmitUint8(0x99);
2126}
2127
2128
Ian Rogers2c8f6532011-09-02 17:16:34 -07002129void X86Assembler::idivl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002130 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2131 EmitUint8(0xF7);
2132 EmitUint8(0xF8 | reg);
2133}
2134
2135
Ian Rogers2c8f6532011-09-02 17:16:34 -07002136void X86Assembler::imull(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002137 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2138 EmitUint8(0x0F);
2139 EmitUint8(0xAF);
2140 EmitOperand(dst, Operand(src));
2141}
2142
2143
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04002144void X86Assembler::imull(Register dst, Register src, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002145 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04002146 // See whether imm can be represented as a sign-extended 8bit value.
2147 int32_t v32 = static_cast<int32_t>(imm.value());
2148 if (IsInt<8>(v32)) {
2149 // Sign-extension works.
2150 EmitUint8(0x6B);
2151 EmitOperand(dst, Operand(src));
2152 EmitUint8(static_cast<uint8_t>(v32 & 0xFF));
2153 } else {
2154 // Not representable, use full immediate.
2155 EmitUint8(0x69);
2156 EmitOperand(dst, Operand(src));
2157 EmitImmediate(imm);
2158 }
2159}
2160
2161
2162void X86Assembler::imull(Register reg, const Immediate& imm) {
2163 imull(reg, reg, imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002164}
2165
2166
Ian Rogers2c8f6532011-09-02 17:16:34 -07002167void X86Assembler::imull(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002168 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2169 EmitUint8(0x0F);
2170 EmitUint8(0xAF);
2171 EmitOperand(reg, address);
2172}
2173
2174
Ian Rogers2c8f6532011-09-02 17:16:34 -07002175void X86Assembler::imull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2177 EmitUint8(0xF7);
2178 EmitOperand(5, Operand(reg));
2179}
2180
2181
Ian Rogers2c8f6532011-09-02 17:16:34 -07002182void X86Assembler::imull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2184 EmitUint8(0xF7);
2185 EmitOperand(5, address);
2186}
2187
2188
Ian Rogers2c8f6532011-09-02 17:16:34 -07002189void X86Assembler::mull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2191 EmitUint8(0xF7);
2192 EmitOperand(4, Operand(reg));
2193}
2194
2195
Ian Rogers2c8f6532011-09-02 17:16:34 -07002196void X86Assembler::mull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002197 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2198 EmitUint8(0xF7);
2199 EmitOperand(4, address);
2200}
2201
2202
Ian Rogers2c8f6532011-09-02 17:16:34 -07002203void X86Assembler::sbbl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002204 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2205 EmitUint8(0x1B);
2206 EmitOperand(dst, Operand(src));
2207}
2208
2209
Ian Rogers2c8f6532011-09-02 17:16:34 -07002210void X86Assembler::sbbl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002211 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2212 EmitComplex(3, Operand(reg), imm);
2213}
2214
2215
Ian Rogers2c8f6532011-09-02 17:16:34 -07002216void X86Assembler::sbbl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002217 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2218 EmitUint8(0x1B);
2219 EmitOperand(dst, address);
2220}
2221
2222
Mark Mendell09ed1a32015-03-25 08:30:06 -04002223void X86Assembler::sbbl(const Address& address, Register src) {
2224 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2225 EmitUint8(0x19);
2226 EmitOperand(src, address);
2227}
2228
2229
Ian Rogers2c8f6532011-09-02 17:16:34 -07002230void X86Assembler::incl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002231 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2232 EmitUint8(0x40 + reg);
2233}
2234
2235
Ian Rogers2c8f6532011-09-02 17:16:34 -07002236void X86Assembler::incl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002237 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2238 EmitUint8(0xFF);
2239 EmitOperand(0, address);
2240}
2241
2242
Ian Rogers2c8f6532011-09-02 17:16:34 -07002243void X86Assembler::decl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002244 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2245 EmitUint8(0x48 + reg);
2246}
2247
2248
Ian Rogers2c8f6532011-09-02 17:16:34 -07002249void X86Assembler::decl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002250 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2251 EmitUint8(0xFF);
2252 EmitOperand(1, address);
2253}
2254
2255
Ian Rogers2c8f6532011-09-02 17:16:34 -07002256void X86Assembler::shll(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00002257 EmitGenericShift(4, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002258}
2259
2260
Ian Rogers2c8f6532011-09-02 17:16:34 -07002261void X86Assembler::shll(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002262 EmitGenericShift(4, Operand(operand), shifter);
2263}
2264
2265
2266void X86Assembler::shll(const Address& address, const Immediate& imm) {
2267 EmitGenericShift(4, address, imm);
2268}
2269
2270
2271void X86Assembler::shll(const Address& address, Register shifter) {
2272 EmitGenericShift(4, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002273}
2274
2275
Ian Rogers2c8f6532011-09-02 17:16:34 -07002276void X86Assembler::shrl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00002277 EmitGenericShift(5, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002278}
2279
2280
Ian Rogers2c8f6532011-09-02 17:16:34 -07002281void X86Assembler::shrl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002282 EmitGenericShift(5, Operand(operand), shifter);
2283}
2284
2285
2286void X86Assembler::shrl(const Address& address, const Immediate& imm) {
2287 EmitGenericShift(5, address, imm);
2288}
2289
2290
2291void X86Assembler::shrl(const Address& address, Register shifter) {
2292 EmitGenericShift(5, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002293}
2294
2295
Ian Rogers2c8f6532011-09-02 17:16:34 -07002296void X86Assembler::sarl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00002297 EmitGenericShift(7, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002298}
2299
2300
Ian Rogers2c8f6532011-09-02 17:16:34 -07002301void X86Assembler::sarl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002302 EmitGenericShift(7, Operand(operand), shifter);
2303}
2304
2305
2306void X86Assembler::sarl(const Address& address, const Immediate& imm) {
2307 EmitGenericShift(7, address, imm);
2308}
2309
2310
2311void X86Assembler::sarl(const Address& address, Register shifter) {
2312 EmitGenericShift(7, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002313}
2314
2315
Calin Juravle9aec02f2014-11-18 23:06:35 +00002316void X86Assembler::shld(Register dst, Register src, Register shifter) {
2317 DCHECK_EQ(ECX, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002318 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2319 EmitUint8(0x0F);
2320 EmitUint8(0xA5);
2321 EmitRegisterOperand(src, dst);
2322}
2323
2324
Mark P Mendell73945692015-04-29 14:56:17 +00002325void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
2326 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2327 EmitUint8(0x0F);
2328 EmitUint8(0xA4);
2329 EmitRegisterOperand(src, dst);
2330 EmitUint8(imm.value() & 0xFF);
2331}
2332
2333
Calin Juravle9aec02f2014-11-18 23:06:35 +00002334void X86Assembler::shrd(Register dst, Register src, Register shifter) {
2335 DCHECK_EQ(ECX, shifter);
2336 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2337 EmitUint8(0x0F);
2338 EmitUint8(0xAD);
2339 EmitRegisterOperand(src, dst);
2340}
2341
2342
Mark P Mendell73945692015-04-29 14:56:17 +00002343void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
2344 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2345 EmitUint8(0x0F);
2346 EmitUint8(0xAC);
2347 EmitRegisterOperand(src, dst);
2348 EmitUint8(imm.value() & 0xFF);
2349}
2350
2351
Mark Mendellbcee0922015-09-15 21:45:01 -04002352void X86Assembler::roll(Register reg, const Immediate& imm) {
2353 EmitGenericShift(0, Operand(reg), imm);
2354}
2355
2356
2357void X86Assembler::roll(Register operand, Register shifter) {
2358 EmitGenericShift(0, Operand(operand), shifter);
2359}
2360
2361
2362void X86Assembler::rorl(Register reg, const Immediate& imm) {
2363 EmitGenericShift(1, Operand(reg), imm);
2364}
2365
2366
2367void X86Assembler::rorl(Register operand, Register shifter) {
2368 EmitGenericShift(1, Operand(operand), shifter);
2369}
2370
2371
Ian Rogers2c8f6532011-09-02 17:16:34 -07002372void X86Assembler::negl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002373 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2374 EmitUint8(0xF7);
2375 EmitOperand(3, Operand(reg));
2376}
2377
2378
Ian Rogers2c8f6532011-09-02 17:16:34 -07002379void X86Assembler::notl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002380 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2381 EmitUint8(0xF7);
2382 EmitUint8(0xD0 | reg);
2383}
2384
2385
Ian Rogers2c8f6532011-09-02 17:16:34 -07002386void X86Assembler::enter(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002387 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2388 EmitUint8(0xC8);
2389 CHECK(imm.is_uint16());
2390 EmitUint8(imm.value() & 0xFF);
2391 EmitUint8((imm.value() >> 8) & 0xFF);
2392 EmitUint8(0x00);
2393}
2394
2395
Ian Rogers2c8f6532011-09-02 17:16:34 -07002396void X86Assembler::leave() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002397 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2398 EmitUint8(0xC9);
2399}
2400
2401
Ian Rogers2c8f6532011-09-02 17:16:34 -07002402void X86Assembler::ret() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002403 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2404 EmitUint8(0xC3);
2405}
2406
2407
Ian Rogers2c8f6532011-09-02 17:16:34 -07002408void X86Assembler::ret(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002409 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2410 EmitUint8(0xC2);
2411 CHECK(imm.is_uint16());
2412 EmitUint8(imm.value() & 0xFF);
2413 EmitUint8((imm.value() >> 8) & 0xFF);
2414}
2415
2416
2417
Ian Rogers2c8f6532011-09-02 17:16:34 -07002418void X86Assembler::nop() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002419 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2420 EmitUint8(0x90);
2421}
2422
2423
Ian Rogers2c8f6532011-09-02 17:16:34 -07002424void X86Assembler::int3() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002425 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2426 EmitUint8(0xCC);
2427}
2428
2429
Ian Rogers2c8f6532011-09-02 17:16:34 -07002430void X86Assembler::hlt() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002431 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2432 EmitUint8(0xF4);
2433}
2434
2435
Ian Rogers2c8f6532011-09-02 17:16:34 -07002436void X86Assembler::j(Condition condition, Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002437 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2438 if (label->IsBound()) {
2439 static const int kShortSize = 2;
2440 static const int kLongSize = 6;
2441 int offset = label->Position() - buffer_.Size();
2442 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002443 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002444 EmitUint8(0x70 + condition);
2445 EmitUint8((offset - kShortSize) & 0xFF);
2446 } else {
2447 EmitUint8(0x0F);
2448 EmitUint8(0x80 + condition);
2449 EmitInt32(offset - kLongSize);
2450 }
2451 } else {
2452 EmitUint8(0x0F);
2453 EmitUint8(0x80 + condition);
2454 EmitLabelLink(label);
2455 }
2456}
2457
2458
Mark Mendell73f455e2015-08-21 09:30:05 -04002459void X86Assembler::j(Condition condition, NearLabel* label) {
2460 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2461 if (label->IsBound()) {
2462 static const int kShortSize = 2;
2463 int offset = label->Position() - buffer_.Size();
2464 CHECK_LE(offset, 0);
2465 CHECK(IsInt<8>(offset - kShortSize));
2466 EmitUint8(0x70 + condition);
2467 EmitUint8((offset - kShortSize) & 0xFF);
2468 } else {
2469 EmitUint8(0x70 + condition);
2470 EmitLabelLink(label);
2471 }
2472}
2473
2474
2475void X86Assembler::jecxz(NearLabel* label) {
2476 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2477 if (label->IsBound()) {
2478 static const int kShortSize = 2;
2479 int offset = label->Position() - buffer_.Size();
2480 CHECK_LE(offset, 0);
2481 CHECK(IsInt<8>(offset - kShortSize));
2482 EmitUint8(0xE3);
2483 EmitUint8((offset - kShortSize) & 0xFF);
2484 } else {
2485 EmitUint8(0xE3);
2486 EmitLabelLink(label);
2487 }
2488}
2489
2490
Ian Rogers2c8f6532011-09-02 17:16:34 -07002491void X86Assembler::jmp(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002492 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2493 EmitUint8(0xFF);
2494 EmitRegisterOperand(4, reg);
2495}
2496
Ian Rogers7caad772012-03-30 01:07:54 -07002497void X86Assembler::jmp(const Address& address) {
2498 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2499 EmitUint8(0xFF);
2500 EmitOperand(4, address);
2501}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002502
Ian Rogers2c8f6532011-09-02 17:16:34 -07002503void X86Assembler::jmp(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002504 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2505 if (label->IsBound()) {
2506 static const int kShortSize = 2;
2507 static const int kLongSize = 5;
2508 int offset = label->Position() - buffer_.Size();
2509 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002510 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002511 EmitUint8(0xEB);
2512 EmitUint8((offset - kShortSize) & 0xFF);
2513 } else {
2514 EmitUint8(0xE9);
2515 EmitInt32(offset - kLongSize);
2516 }
2517 } else {
2518 EmitUint8(0xE9);
2519 EmitLabelLink(label);
2520 }
2521}
2522
2523
Mark Mendell73f455e2015-08-21 09:30:05 -04002524void X86Assembler::jmp(NearLabel* label) {
2525 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2526 if (label->IsBound()) {
2527 static const int kShortSize = 2;
2528 int offset = label->Position() - buffer_.Size();
2529 CHECK_LE(offset, 0);
2530 CHECK(IsInt<8>(offset - kShortSize));
2531 EmitUint8(0xEB);
2532 EmitUint8((offset - kShortSize) & 0xFF);
2533 } else {
2534 EmitUint8(0xEB);
2535 EmitLabelLink(label);
2536 }
2537}
2538
2539
jessicahandojob03d6402016-09-07 12:16:53 -07002540void X86Assembler::repne_scasb() {
2541 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2542 EmitUint8(0xF2);
2543 EmitUint8(0xAE);
2544}
2545
2546
Andreas Gampe21030dd2015-05-07 14:46:15 -07002547void X86Assembler::repne_scasw() {
2548 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2549 EmitUint8(0x66);
2550 EmitUint8(0xF2);
2551 EmitUint8(0xAF);
2552}
2553
2554
jessicahandojob03d6402016-09-07 12:16:53 -07002555void X86Assembler::repe_cmpsb() {
2556 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2557 EmitUint8(0xF2);
2558 EmitUint8(0xA6);
2559}
2560
2561
agicsaki71311f82015-07-27 11:34:13 -07002562void X86Assembler::repe_cmpsw() {
2563 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2564 EmitUint8(0x66);
2565 EmitUint8(0xF3);
2566 EmitUint8(0xA7);
2567}
2568
2569
agicsaki970abfb2015-07-31 10:31:14 -07002570void X86Assembler::repe_cmpsl() {
2571 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2572 EmitUint8(0xF3);
2573 EmitUint8(0xA7);
2574}
2575
2576
jessicahandojob03d6402016-09-07 12:16:53 -07002577void X86Assembler::rep_movsb() {
2578 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2579 EmitUint8(0xF3);
2580 EmitUint8(0xA4);
2581}
2582
2583
Mark Mendellb9c4bbe2015-07-01 14:26:52 -04002584void X86Assembler::rep_movsw() {
2585 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2586 EmitUint8(0x66);
2587 EmitUint8(0xF3);
2588 EmitUint8(0xA5);
2589}
2590
2591
Ian Rogers2c8f6532011-09-02 17:16:34 -07002592X86Assembler* X86Assembler::lock() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002593 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2594 EmitUint8(0xF0);
Ian Rogers0d666d82011-08-14 16:03:46 -07002595 return this;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002596}
2597
2598
Ian Rogers2c8f6532011-09-02 17:16:34 -07002599void X86Assembler::cmpxchgl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002600 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2601 EmitUint8(0x0F);
2602 EmitUint8(0xB1);
2603 EmitOperand(reg, address);
2604}
2605
Mark Mendell58d25fd2015-04-03 14:52:31 -04002606
2607void X86Assembler::cmpxchg8b(const Address& address) {
2608 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2609 EmitUint8(0x0F);
2610 EmitUint8(0xC7);
2611 EmitOperand(1, address);
2612}
2613
2614
Elliott Hughes79ab9e32012-03-12 15:41:35 -07002615void X86Assembler::mfence() {
2616 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2617 EmitUint8(0x0F);
2618 EmitUint8(0xAE);
2619 EmitUint8(0xF0);
2620}
2621
Ian Rogers2c8f6532011-09-02 17:16:34 -07002622X86Assembler* X86Assembler::fs() {
Ian Rogersb033c752011-07-20 12:22:35 -07002623 // TODO: fs is a prefix and not an instruction
2624 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2625 EmitUint8(0x64);
Ian Rogers0d666d82011-08-14 16:03:46 -07002626 return this;
Ian Rogersb033c752011-07-20 12:22:35 -07002627}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002628
Ian Rogersbefbd572014-03-06 01:13:39 -08002629X86Assembler* X86Assembler::gs() {
2630 // TODO: fs is a prefix and not an instruction
2631 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2632 EmitUint8(0x65);
2633 return this;
2634}
2635
Ian Rogers2c8f6532011-09-02 17:16:34 -07002636void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002637 int value = imm.value();
2638 if (value > 0) {
2639 if (value == 1) {
2640 incl(reg);
2641 } else if (value != 0) {
2642 addl(reg, imm);
2643 }
2644 } else if (value < 0) {
2645 value = -value;
2646 if (value == 1) {
2647 decl(reg);
2648 } else if (value != 0) {
2649 subl(reg, Immediate(value));
2650 }
2651 }
2652}
2653
2654
Roland Levillain647b9ed2014-11-27 12:06:00 +00002655void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) {
2656 // TODO: Need to have a code constants table.
2657 pushl(Immediate(High32Bits(value)));
2658 pushl(Immediate(Low32Bits(value)));
2659 movsd(dst, Address(ESP, 0));
2660 addl(ESP, Immediate(2 * sizeof(int32_t)));
2661}
2662
2663
Ian Rogers2c8f6532011-09-02 17:16:34 -07002664void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002665 // TODO: Need to have a code constants table.
2666 int64_t constant = bit_cast<int64_t, double>(value);
Roland Levillain647b9ed2014-11-27 12:06:00 +00002667 LoadLongConstant(dst, constant);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002668}
2669
2670
Ian Rogers2c8f6532011-09-02 17:16:34 -07002671void X86Assembler::Align(int alignment, int offset) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002672 CHECK(IsPowerOfTwo(alignment));
2673 // Emit nop instruction until the real position is aligned.
2674 while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
2675 nop();
2676 }
2677}
2678
2679
Ian Rogers2c8f6532011-09-02 17:16:34 -07002680void X86Assembler::Bind(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002681 int bound = buffer_.Size();
2682 CHECK(!label->IsBound()); // Labels can only be bound once.
2683 while (label->IsLinked()) {
2684 int position = label->LinkPosition();
2685 int next = buffer_.Load<int32_t>(position);
2686 buffer_.Store<int32_t>(position, bound - (position + 4));
2687 label->position_ = next;
2688 }
2689 label->BindTo(bound);
2690}
2691
2692
Mark Mendell73f455e2015-08-21 09:30:05 -04002693void X86Assembler::Bind(NearLabel* label) {
2694 int bound = buffer_.Size();
2695 CHECK(!label->IsBound()); // Labels can only be bound once.
2696 while (label->IsLinked()) {
2697 int position = label->LinkPosition();
2698 uint8_t delta = buffer_.Load<uint8_t>(position);
2699 int offset = bound - (position + 1);
2700 CHECK(IsInt<8>(offset));
2701 buffer_.Store<int8_t>(position, offset);
2702 label->position_ = delta != 0u ? label->position_ - delta : 0;
2703 }
2704 label->BindTo(bound);
2705}
2706
2707
Ian Rogers44fb0d02012-03-23 16:46:24 -07002708void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
2709 CHECK_GE(reg_or_opcode, 0);
2710 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002711 const int length = operand.length_;
2712 CHECK_GT(length, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002713 // Emit the ModRM byte updated with the given reg value.
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002714 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002715 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002716 // Emit the rest of the encoded operand.
2717 for (int i = 1; i < length; i++) {
2718 EmitUint8(operand.encoding_[i]);
2719 }
Mark Mendell0616ae02015-04-17 12:49:27 -04002720 AssemblerFixup* fixup = operand.GetFixup();
2721 if (fixup != nullptr) {
2722 EmitFixup(fixup);
2723 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002724}
2725
2726
Ian Rogers2c8f6532011-09-02 17:16:34 -07002727void X86Assembler::EmitImmediate(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002728 EmitInt32(imm.value());
2729}
2730
2731
Ian Rogers44fb0d02012-03-23 16:46:24 -07002732void X86Assembler::EmitComplex(int reg_or_opcode,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002733 const Operand& operand,
2734 const Immediate& immediate) {
Ian Rogers44fb0d02012-03-23 16:46:24 -07002735 CHECK_GE(reg_or_opcode, 0);
2736 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002737 if (immediate.is_int8()) {
2738 // Use sign-extended 8-bit immediate.
2739 EmitUint8(0x83);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002740 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002741 EmitUint8(immediate.value() & 0xFF);
2742 } else if (operand.IsRegister(EAX)) {
2743 // Use short form if the destination is eax.
Ian Rogers44fb0d02012-03-23 16:46:24 -07002744 EmitUint8(0x05 + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002745 EmitImmediate(immediate);
2746 } else {
2747 EmitUint8(0x81);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002748 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002749 EmitImmediate(immediate);
2750 }
2751}
2752
2753
Ian Rogers2c8f6532011-09-02 17:16:34 -07002754void X86Assembler::EmitLabel(Label* label, int instruction_size) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002755 if (label->IsBound()) {
2756 int offset = label->Position() - buffer_.Size();
2757 CHECK_LE(offset, 0);
2758 EmitInt32(offset - instruction_size);
2759 } else {
2760 EmitLabelLink(label);
2761 }
2762}
2763
2764
Ian Rogers2c8f6532011-09-02 17:16:34 -07002765void X86Assembler::EmitLabelLink(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002766 CHECK(!label->IsBound());
2767 int position = buffer_.Size();
2768 EmitInt32(label->position_);
2769 label->LinkTo(position);
2770}
2771
2772
Mark Mendell73f455e2015-08-21 09:30:05 -04002773void X86Assembler::EmitLabelLink(NearLabel* label) {
2774 CHECK(!label->IsBound());
2775 int position = buffer_.Size();
2776 if (label->IsLinked()) {
2777 // Save the delta in the byte that we have to play with.
2778 uint32_t delta = position - label->LinkPosition();
2779 CHECK(IsUint<8>(delta));
2780 EmitUint8(delta & 0xFF);
2781 } else {
2782 EmitUint8(0);
2783 }
2784 label->LinkTo(position);
2785}
2786
2787
Ian Rogers44fb0d02012-03-23 16:46:24 -07002788void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002789 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002790 const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002791 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2792 CHECK(imm.is_int8());
2793 if (imm.value() == 1) {
2794 EmitUint8(0xD1);
Mark P Mendell73945692015-04-29 14:56:17 +00002795 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002796 } else {
2797 EmitUint8(0xC1);
Mark P Mendell73945692015-04-29 14:56:17 +00002798 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002799 EmitUint8(imm.value() & 0xFF);
2800 }
2801}
2802
2803
Ian Rogers44fb0d02012-03-23 16:46:24 -07002804void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002805 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002806 Register shifter) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002807 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2808 CHECK_EQ(shifter, ECX);
2809 EmitUint8(0xD3);
Mark P Mendell73945692015-04-29 14:56:17 +00002810 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002811}
2812
Mark Mendell0616ae02015-04-17 12:49:27 -04002813void X86Assembler::AddConstantArea() {
Vladimir Marko93205e32016-04-13 11:59:46 +01002814 ArrayRef<const int32_t> area = constant_area_.GetBuffer();
Mark Mendell0616ae02015-04-17 12:49:27 -04002815 // Generate the data for the literal area.
2816 for (size_t i = 0, e = area.size(); i < e; i++) {
2817 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2818 EmitInt32(area[i]);
2819 }
2820}
2821
Mark Mendell805b3b52015-09-18 14:10:29 -04002822size_t ConstantArea::AppendInt32(int32_t v) {
2823 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002824 buffer_.push_back(v);
2825 return result;
2826}
2827
Mark Mendell805b3b52015-09-18 14:10:29 -04002828size_t ConstantArea::AddInt32(int32_t v) {
2829 for (size_t i = 0, e = buffer_.size(); i < e; i++) {
2830 if (v == buffer_[i]) {
2831 return i * elem_size_;
2832 }
2833 }
2834
2835 // Didn't match anything.
2836 return AppendInt32(v);
2837}
2838
2839size_t ConstantArea::AddInt64(int64_t v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002840 int32_t v_low = Low32Bits(v);
2841 int32_t v_high = High32Bits(v);
2842 if (buffer_.size() > 1) {
2843 // Ensure we don't pass the end of the buffer.
2844 for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) {
2845 if (v_low == buffer_[i] && v_high == buffer_[i + 1]) {
Mark Mendell805b3b52015-09-18 14:10:29 -04002846 return i * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002847 }
2848 }
2849 }
2850
2851 // Didn't match anything.
Mark Mendell805b3b52015-09-18 14:10:29 -04002852 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002853 buffer_.push_back(v_low);
2854 buffer_.push_back(v_high);
2855 return result;
2856}
2857
Mark Mendell805b3b52015-09-18 14:10:29 -04002858size_t ConstantArea::AddDouble(double v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002859 // Treat the value as a 64-bit integer value.
2860 return AddInt64(bit_cast<int64_t, double>(v));
2861}
2862
Mark Mendell805b3b52015-09-18 14:10:29 -04002863size_t ConstantArea::AddFloat(float v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002864 // Treat the value as a 32-bit integer value.
2865 return AddInt32(bit_cast<int32_t, float>(v));
2866}
2867
Ian Rogers2c8f6532011-09-02 17:16:34 -07002868} // namespace x86
Ian Rogersb033c752011-07-20 12:22:35 -07002869} // namespace art