| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 1 | #/** @file
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| 2 | #
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| Olivier Martin | 5c2d456 | 2015-01-06 15:54:12 +0000 | [diff] [blame] | 3 | # Copyright (c) 2011-2015, ARM Limited. All rights reserved.
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 4 | #
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| Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 5 | # This program and the accompanying materials
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| 6 | # are licensed and made available under the terms and conditions of the BSD License
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| 7 | # which accompanies this distribution. The full text of the license may be found at
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| 8 | # http://opensource.org/licenses/bsd-license.php
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| 9 | #
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| 10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 12 | #
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| 13 | #**/
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| 14 |
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| 15 | [Defines]
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| 16 | DEC_SPECIFICATION = 0x00010005
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| 17 | PACKAGE_NAME = ArmPlatformPkg
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| Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 18 | PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 19 | PACKAGE_VERSION = 0.1
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| 20 |
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| 21 | ################################################################################
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| 22 | #
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| 23 | # Include Section - list of Include Paths that are provided by this package.
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| 24 | # Comments are used for Keywords and Module Types.
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| 25 | #
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| 26 | # Supported Module Types:
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| 27 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
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| 28 | #
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| 29 | ################################################################################
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| 30 | [Includes.common]
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| 31 | Include # Root include for the package
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| 32 |
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| 33 | [Guids.common]
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| 34 | gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
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| 35 | #
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| 36 | # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
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| 37 | #
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| 38 | gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }
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| Ard Biesheuvel | 6cf1269 | 2015-05-07 15:18:14 +0000 | [diff] [blame] | 39 | #
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| 40 | # Following Guid must match FILE_GUID in SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableRuntimeDxe.inf
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| 41 | #
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| 42 | gVariableAuthenticatedRuntimeDxeFileGuid = { 0x2226f30f, 0x3d5b, 0x402d, {0x99, 0x36, 0xa9, 0x71, 0x84, 0xEB, 0x45, 0x16 } }
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 43 |
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| oliviermartin | 8fc38a3 | 2011-09-22 23:11:03 +0000 | [diff] [blame] | 44 | ## Include/Guid/ArmGlobalVariableHob.h
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| 45 | gArmGlobalVariableGuid = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }
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| 46 |
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| Harry Liebel | da5daf3 | 2014-08-26 10:15:21 +0000 | [diff] [blame] | 47 | gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }
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| 48 |
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| oliviermartin | 8fc38a3 | 2011-09-22 23:11:03 +0000 | [diff] [blame] | 49 | [Ppis]
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| 50 | ## Include/Ppi/ArmGlobalVariable.h
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| 51 | gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }
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| 52 |
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 53 | [PcdsFeatureFlag.common]
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| 54 | # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
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| 55 | gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
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| Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 56 |
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 57 | gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
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| 58 | gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002
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| 59 | gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
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| 60 |
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| oliviermartin | 68dda85 | 2012-02-28 17:32:47 +0000 | [diff] [blame] | 61 | gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C
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| Olivier Martin | d8c4bb9 | 2013-09-23 09:40:27 +0000 | [diff] [blame] | 62 |
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| 63 | # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,
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| 64 | # we assume the OS will handle the FrameBuffer from the UEFI GOP information.
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| 65 | gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D
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| 66 |
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 67 | [PcdsFixedAtBuild.common]
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| oliviermartin | 695df8b | 2012-09-28 10:43:28 +0000 | [diff] [blame] | 68 | gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039
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| oliviermartin | 2dbcb8f | 2011-09-22 23:05:20 +0000 | [diff] [blame] | 69 | gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
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| Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 70 |
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 71 | # Stack for CPU Cores in Secure Mode
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| 72 | gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005
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| oliviermartin | 2dbcb8f | 2011-09-22 23:05:20 +0000 | [diff] [blame] | 73 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036
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| 74 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 75 |
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 76 | # Stack for CPU Cores in Non Secure Mode
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| Leif Lindholm | bb5420b | 2014-11-11 00:43:03 +0000 | [diff] [blame] | 77 | gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009
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| oliviermartin | 2dbcb8f | 2011-09-22 23:05:20 +0000 | [diff] [blame] | 78 | gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
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| 79 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A
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| Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 80 |
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 81 | # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
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| 82 | gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
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| 83 |
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| 84 | # Size to reserve in the primary core stack for PEI Global Variables
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| 85 | # = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */
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| 86 | gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016
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| 87 | # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list
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| Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 88 | # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 89 | gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017
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| 90 | gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018
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| 91 |
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| oliviermartin | 8fc38a3 | 2011-09-22 23:11:03 +0000 | [diff] [blame] | 92 | # Size to reserve in the primary core stack for SEC Global Variables
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| 93 | gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031
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| 94 |
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| Olivier Martin | 94e0955 | 2014-01-16 00:06:13 +0000 | [diff] [blame] | 95 | # Boot Monitor FileSystem
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| 96 | gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A
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| 97 |
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 98 | #
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| 99 | # ARM Primecells
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| 100 | #
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| 101 |
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| 102 | ## SP804 DualTimer
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| 103 | gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D
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| 104 | gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E
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| 105 | gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A
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| 106 | gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B
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| 107 | gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C
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| 108 |
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| 109 | ## SP805 Watchdog
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| 110 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
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| 111 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
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| 112 |
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| 113 | ## PL011 UART
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| oliviermartin | 051e63b | 2012-02-29 17:19:52 +0000 | [diff] [blame] | 114 | gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F
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| 115 | gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020
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| 116 | gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 117 |
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 118 | ## PL061 GPIO
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| 119 | gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
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| Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 120 |
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| oliviermartin | 9862239 | 2012-02-28 17:09:16 +0000 | [diff] [blame] | 121 | ## PL111 Lcd & HdLcd
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 122 | gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026
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| 123 | gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027
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| Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 124 |
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 125 | ## PL180 MCI
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| 126 | gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028
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| 127 | gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029
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| 128 |
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| 129 | #
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| 130 | # BDS - Boot Manager
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| 131 | #
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| 132 | gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019
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| 133 | gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C
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| 134 | gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D
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| 135 | gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E
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| Olivier Martin | 6bcedce | 2014-04-11 10:59:06 +0000 | [diff] [blame] | 136 | gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F
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| Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 137 | # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath:
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 138 | # - 0 = an EFI application
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| 139 | # - 1 = a Linux kernel with ATAG support
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| 140 | # - 2 = a Linux kernel with FDT support
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| 141 | gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010
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| Ronald Cron | 3402aac | 2014-08-19 13:29:52 +0000 | [diff] [blame] | 142 |
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| oliviermartin | 11c20f4 | 2011-09-22 22:53:54 +0000 | [diff] [blame] | 143 | gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
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| 144 | gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C
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| Harry Liebel | 1bc8326 | 2013-07-18 19:06:52 +0000 | [diff] [blame] | 145 |
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| Ard Biesheuvel | b4e2799 | 2014-09-01 15:58:51 +0000 | [diff] [blame] | 146 | [PcdsFixedAtBuild.common,PcdsDynamic.common]
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| 147 | ## PL031 RealTimeClock
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| 148 | gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
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| 149 | gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
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| 150 |
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| Laszlo Ersek | e48f1f1 | 2015-02-23 16:02:44 +0000 | [diff] [blame] | 151 | #
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| 152 | # Inclusive range of allowed PCI buses.
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| 153 | #
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| 154 | gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E
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| 155 | gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F
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| 156 |
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| 157 | #
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| 158 | # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
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| 159 | # Note that "IO" is just another MMIO range that simulates IO space; there
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| 160 | # are no special instructions to access it.
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| 161 | #
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| 162 | # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
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| 163 | # specific to their containing address spaces. In order to get the physical
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| 164 | # address for the CPU, for a given access, the respective translation value
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| 165 | # has to be added.
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| 166 | #
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| 167 | # The translations always have to be initialized like this, using UINT64:
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| 168 | #
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| 169 | # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
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| 170 | # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
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| 171 | # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
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| 172 | #
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| 173 | # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
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| 174 | # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
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| 175 | # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
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| 176 | #
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| 177 | # because (a) the target address space (ie. the cpu-physical space) is
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| 178 | # 64-bit, and (b) the translation values are meant as offsets for *modular*
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| 179 | # arithmetic.
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| 180 | #
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| 181 | # Accordingly, the translation itself needs to be implemented as:
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| 182 | #
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| 183 | # UINT64 UntranslatedIoAddress; // input parameter
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| 184 | # UINT32 UntranslatedMmio32Address; // input parameter
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| 185 | # UINT64 UntranslatedMmio64Address; // input parameter
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| 186 | #
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| 187 | # UINT64 TranslatedIoAddress; // output parameter
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| 188 | # UINT64 TranslatedMmio32Address; // output parameter
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| 189 | # UINT64 TranslatedMmio64Address; // output parameter
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| 190 | #
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| 191 | # TranslatedIoAddress = UntranslatedIoAddress +
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| 192 | # PcdPciIoTranslation;
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| 193 | # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
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| 194 | # PcdPciMmio32Translation;
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| 195 | # TranslatedMmio64Address = UntranslatedMmio64Address +
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| 196 | # PcdPciMmio64Translation;
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| 197 | #
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| 198 | # The modular arithmetic performed in UINT64 ensures that the translation
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| 199 | # works correctly regardless of the relation between IoCpuBase and
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| 200 | # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
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| 201 | # PcdPciMmio64Base.
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| 202 | #
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| 203 | gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040
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| 204 | gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041
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| 205 | gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042
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| 206 | gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043
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| 207 | gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044
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| 208 | gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045
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| 209 | gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046
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| 210 | gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047
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| 211 | gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048
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| 212 |
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| Harry Liebel | 1bc8326 | 2013-07-18 19:06:52 +0000 | [diff] [blame] | 213 | [PcdsFixedAtBuild.ARM]
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| 214 | # Stack for CPU Cores in Secure Monitor Mode
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| 215 | gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
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| 216 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008
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| 217 |
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| 218 | [PcdsFixedAtBuild.AARCH64]
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| 219 | # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.
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| 220 | # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize
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| 221 | # and PcdCPUCoreSecSecondaryStackSize
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| 222 | gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
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| 223 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008
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| 224 |
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