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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / ec7f9844ef90ee3ac18194f24fa478577dcfc4ae / drivers / clk / sunxi-ng / ccu-sun8i-a33.c
  1. 372fa10 clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change by Chen-Yu Tsai · 8 years ago
  2. 64afa89 clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU by Maxime Ripard · 8 years ago
  3. 603a0c8 clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-dig by Mylène Josserand · 8 years ago
  4. bb021cd clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33 by Icenowy Zheng · 8 years ago
  5. 790d929 clk: sunxi-ng: fix PLL_CPUX adjusting on A33 by Icenowy Zheng · 8 years ago
  6. 98fb2b9 clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock by Icenowy Zheng · 8 years ago
  7. 5519cf2 clk: sunxi-ng: Fix reset offset for the A23 and A33 by Maxime Ripard · 8 years ago
  8. d05c748 clk: sunxi-ng: Add A33 CCU support by Maxime Ripard · 9 years ago