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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / d2e11fd2b7fcd10b7bcef418c55490c934aa94e8 / drivers / clocksource / timer-riscv.c
  1. 2bc3fc8 RISC-V: Remove CLINT related code from timer and arch by Anup Patel · 4 years, 7 months ago
  2. 033a65d clocksource/drivers/timer-riscv: Use per-CPU timer interrupt by Anup Patel · 4 years, 10 months ago
  3. 9d05c18 clocksource: riscv: add notrace to riscv_sched_clock by Zong Li · 5 years ago
  4. 4f9bbce riscv: add support for MMIO access to the timer registers by Christoph Hellwig · 5 years ago
  5. a4c3733 riscv: abstract out CSR names for supervisor vs machine mode by Christoph Hellwig · 5 years ago
  6. 2f12dbf1 riscv: don't use the rdtime(h) pseudo-instructions by Christoph Hellwig · 6 years ago
  7. 713203e RISC-V: Remove per cpu clocksource by Atish Patra · 6 years ago
  8. 32d0be0 clocksource/drivers/riscv: Fix clocksource mask by Atish Patra · 6 years ago
  9. 26478b2 clocksource/drivers/riscv: Add required checks during clock source init by Atish Patra · 6 years ago
  10. 3d42b32 clocksource/drivers/riscv: Change name riscv_timer to timer-riscv by Daniel Lezcano · 6 years ago[Renamed from drivers/clocksource/riscv_timer.c]
  11. 92e0d14 clocksource/drivers/riscv_timer: Provide the sched_clock by Anup Patel · 6 years ago
  12. f99fb60 RISC-V: Use Linux logical CPU number instead of hartid by Atish Patra · 6 years ago
  13. b2f8cfa7 RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid by Palmer Dabbelt · 6 years ago
  14. 62b0194 clocksource: new RISC-V SBI timer driver by Palmer Dabbelt · 7 years ago