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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 9414f563f3857018d87e480b7cd13636b0c00ce6 / drivers / gpu / drm / i915 / intel_pm.c
  1. 9414f56 drm/i915/skl: Rework when the transition WMs are computed by Damien Lespiau · 10 years ago
  2. 407b50f drm/i915/skl: Move all the WM compute functions in one place by Damien Lespiau · 10 years ago
  3. e6d6617 drm/i915/skl: Make res_blocks/lines intermediate values 32 bits by Damien Lespiau · 10 years ago
  4. 21fca25 drm/i915/skl: Use a more descriptive parameter name in skl_compute_plane_wm() by Damien Lespiau · 10 years ago
  5. 16160e3 drm/i915/skl: Make 'end' of the DDB allocation entry exclusive by Damien Lespiau · 10 years ago
  6. 08db665 drm/i915/skl: Check the DDB state at modeset by Damien Lespiau · 10 years ago
  7. a269c58 drm/i915/skl: Read back the DDB allocation hw state by Damien Lespiau · 10 years ago
  8. 53b0deb drm/i915/skl: Store the new WM state at the very end of the update by Damien Lespiau · 10 years ago
  9. 4f94738 drm/i915/gen9: Disable WM if corresponding latency is 0 by Vandana Kannan · 10 years ago
  10. 367294b drm/i915/gen9: Add 2us read latency to WM level by Vandana Kannan · 10 years ago
  11. 3078999 drm/i915/skl: Read the pipe WM HW state by Pradeep Bhat · 10 years ago
  12. 8211bd5 drm/i915/skl: Program the DDB allocation by Damien Lespiau · 10 years ago
  13. b9cec07 drm/i915/skl: Allocate DDB portions for display planes by Damien Lespiau · 10 years ago
  14. 2d41c0b drm/i915/skl: SKL Watermark Computation by Pradeep Bhat · 10 years ago
  15. 2ac96d2 drm/i915/skl: Definition of SKL WM param structs for pipe/plane by Pradeep Bhat · 10 years ago
  16. 2af30a5 drm/i915/skl: Read the Memory Latency Values for WM computation by Pradeep Bhat · 10 years ago
  17. 5e56ba4 drm/i915/chv: Use 16 and 32 for low and high drain latency precision. by Rodrigo Vivi · 10 years ago
  18. 101b376 drm/i915/bdw: Remove BDW preproduction W/As until C stepping. by Rodrigo Vivi · 10 years ago
  19. 58abf1d drm/i915: Do not export RC6p and RC6pp if they don't exist by Rodrigo Vivi · 10 years ago
  20. a8cbd45 Merge branch 'drm-intel-next-fixes' into drm-intel-next by Daniel Vetter · 10 years ago
  21. 2aeb7d3 drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/ by Daniel Vetter · 10 years ago
  22. 9c065a7 drm/i915: Extract intel_runtime_pm.c by Daniel Vetter · 10 years ago
  23. 955e36d Merge branch 'topic/skl-stage1' into drm-intel-next-queued by Daniel Vetter · 10 years ago
  24. 6795686 drm/i915: Don't spam dmesg with rps messages on vlv/chv by Ville Syrjälä · 10 years ago
  25. 7526ed7 Revert "drm/i915/bdw: BDW Software Turbo" by Daniel Vetter · 10 years ago
  26. 1d73c2a drm/i915: Minimize the huge amount of unecessary fbc sw cache clean. by Rodrigo Vivi · 10 years ago
  27. c83155a drm/i915/skl: Move gen9 pm initialization into its own branch by Damien Lespiau · 11 years ago
  28. 3ca5da4 drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:skl by Damien Lespiau · 11 years ago
  29. 91e41d1 drm/i915/skl: Implement Wa4x4STCOptimizationDisable:skl by Damien Lespiau · 11 years ago
  30. acd5c34 drm/i915/skl: Implement WaDisableSDEUnitClockGating:skl by Damien Lespiau · 11 years ago
  31. 08524a9f drm/i915/skl: Restore pipe B/C interrupts by Satheeshakrishna M · 11 years ago
  32. da2078c drm/i915/skl: Provide a placeholder for init_clock_gating() by Damien Lespiau · 12 years ago
  33. 9adccc6 drm/i915: add SW tracking to FBC enabling by Paulo Zanoni · 10 years ago
  34. d2dee86 drm/i915: extract intel_init_fbc() by Paulo Zanoni · 10 years ago
  35. 342e36c drm/i915: Avoid reading fbc registers in vain when fbc was never enabled. by Rodrigo Vivi · 10 years ago
  36. 01d06e9 drm/i915: Only flush fbc on sw when fbc is enabled. by Rodrigo Vivi · 10 years ago
  37. d6feb19 drm/i915: Limit the watermark to at least 8 entries on gen2/3 by Ville Syrjälä · 10 years ago
  38. 773538e8 drm/i915: Reset power sequencer pipe tracking when disp2d is off by Ville Syrjälä · 10 years ago
  39. 5aef600 drm/i915: Rename global latency_ns variable by Chris Wilson · 10 years ago
  40. 1038392 drm/i915: Disable trickle feed for gen2/3 by Ville Syrjälä · 10 years ago
  41. 9d53910 drm/i915: Fix gen2 planes B and C max watermark value by Ville Syrjälä · 10 years ago
  42. 00e1e62 drm/i915: Init some CHV workarounds via LRIs in ring->init_context() by Ville Syrjälä · 10 years ago
  43. 1c14762 drm/i915: Warn about odd rps values on CHV by Ville Syrjälä · 10 years ago
  44. c76bb61 drm/i915/bdw: BDW Software Turbo by Daisy Sun · 10 years ago
  45. 2bb25c1 drm/i915: Populate mem_freq in init_gt_powerwave() by Ville Syrjälä · 10 years ago
  46. 86d7f23 drm/i915/bdw: Apply workarounds in render ring init function by Arun Siluvery · 10 years ago
  47. c5ad011 drm/i915: FBC flush nuke for BDW by Rodrigo Vivi · 10 years ago
  48. 47c2bd9 drm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gating by Paulo Zanoni · 10 years ago
  49. 89d6b2b drm/i915: call lpt_init_clock_gating on BDW too by Paulo Zanoni · 10 years ago
  50. 98a2e5f drm/i915: Bring UP Power Wells before disabling RC6. by Deepak S · 10 years ago
  51. 055e393 drm/i915: Use dev_priv as first argument of for_each_pipe() by Damien Lespiau · 10 years ago
  52. 48404c1 drm/i915: Add 180 degree primary plane rotation support by Sonika Jindal · 10 years ago
  53. a18b29f Merge tag 'drm-intel-next-2014-09-01' of git://anongit.freedesktop.org/drm-intel into drm-next by Dave Airlie · 10 years ago
  54. d5a0f2e Merge tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-intel into drm-next by Dave Airlie · 10 years ago
  55. 1bee201 drm/i915: Remove set but unused 'gt_perf_status' by Damien Lespiau · 10 years ago
  56. 889fa782 Merge tag 'drm-intel-fixes-2014-08-08' of git://anongit.freedesktop.org/drm-intel by Linus Torvalds · 10 years ago
  57. 01e184c drm/i915: Add sprite watermark programming for VLV and CHV by Gajanan Bhat · 10 years ago
  58. a398e9c drm/i915: Round-up clock and limit drain latency by Gajanan Bhat · 10 years ago
  59. 0948c26 drm/i915: Generalize drain latency computation by Gajanan Bhat · 10 years ago
  60. efd814b drm/i915: Polish the chv cmnlane resrt macros by Ville Syrjälä · 11 years ago
  61. 3dd7b974 drm/i915: Hack to tie both common lanes together on chv by Ville Syrjälä · 11 years ago
  62. 3c2777f drm/i915: Add cherryview_update_wm() by Ville Syrjälä · 11 years ago
  63. 41aad81 drm/i915: Update DDL only for current CRTC by Gajanan Bhat · 10 years ago
  64. 1abc4dc drm/i915: Parametrize VLV_DDL registers by Ville Syrjälä · 11 years ago
  65. 0a56067 drm/i915: Fill out the FWx watermark register defines by Ville Syrjälä · 11 years ago
  66. da46f93 drm/i915: Introduce FBC False Color for debug purposes. by Rodrigo Vivi · 10 years ago
  67. a504345 drm/i915: Split a few long debug prints by Ville Syrjälä · 11 years ago
  68. 2ce147f drm/i915: Add chv port D TX wells by Ville Syrjälä · 11 years ago
  69. 8258356 drm/i915: Add chv port B and C TX wells by Ville Syrjälä · 11 years ago
  70. 26972b0 drm/i915: Add per-pipe power wells for chv by Ville Syrjälä · 11 years ago
  71. f07057d drm/i915: Add disp2d power well for chv by Ville Syrjälä · 11 years ago
  72. 5d6f7ea drm/i915: Add chv cmnlane power wells by Ville Syrjälä · 11 years ago
  73. 4811ff4 drm/i915: Add chv_power_wells[] by Ville Syrjälä · 11 years ago
  74. a7d7a14 Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux by Linus Torvalds · 10 years ago
  75. 69bbeb4 drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values by Ville Syrjälä · 11 years ago
  76. 22c5aee drm/i915: Fix drain latency precision multipler for VLV by Zhenyu Wang · 11 years ago
  77. df662a2 drm/i915: Tune down MCH_SSKPD values warning by Daniel Vetter · 10 years ago
  78. 8dfd1f0 drm/i915: Tune done rc6 enabling output by Daniel Vetter · 10 years ago
  79. 5ed0bdf drm: i915: Use nsec based interfaces by Thomas Gleixner · 10 years ago
  80. 9df7575f drm/i915: add helper for checking whether IRQs are enabled by Jesse Barnes · 11 years ago
  81. d49bdb0 drm/i915: extract and improve gen8_irq_power_well_post_enable by Paulo Zanoni · 10 years ago
  82. 480c803 drm/i915: Use genX_ prefix for gt irq enable/disable functions by Daniel Vetter · 10 years ago
  83. ed57cb8 drm/i915: Also give the sprite width for WM computation by Damien Lespiau · 10 years ago
  84. 3463811 drm/i915/chv: Drop WaGsvBringDownFreqInRc6 by Deepak S · 11 years ago
  85. b47adc1 drm/i915: Force GPU Freq to lowest while suspending. by Deepak S · 11 years ago
  86. b55dd64 drm/i915: byt_gpu_freq() can be static by Fengguang Wu · 10 years ago
  87. 7707df4 drm/i915: Add RP1 render P state thresholds in CHV by Deepak S · 10 years ago
  88. 3497a56 drm/i915/chv: Add basic PM interrupt support for CHV by Deepak S · 10 years ago
  89. 22b1b2f drm/i915: CHV GPU frequency to opcode functions by Deepak S · 10 years ago
  90. 67c3bf6 drm/i915: populate mem_freq/cz_clock for chv by Deepak S · 10 years ago
  91. f8f2b00 drm/i915: Read guaranteed freq for valleyview by Deepak S · 10 years ago
  92. 03af204 drm/i915: Use the cached min/min/rpe values in the vlv debugfs code by Ville Syrjälä · 11 years ago
  93. 7b3c29f drm/i915: Make the RPS interrupt generation mask handle the vlv wa by Chris Wilson · 10 years ago
  94. bd2bb1b drm/i915: add POWER_DOMAIN_PLLS by Paulo Zanoni · 10 years ago
  95. 2ff8fde drm/i915: Make use of intel_fb_obj() (v2) by Matt Roper · 10 years ago
  96. 31685c2 drm/i915/vlv: WA for Turbo and RC6 to work together. by Deepak S · 10 years ago
  97. b3f9ad9 drm/i915/bdw: 3D_CHICKEN3 has write mask bits by Michel Thierry · 10 years ago
  98. 9858425 drm/i915: gmch: set SR WMs to valid values before enabling them by Imre Deak · 11 years ago
  99. 5209b1f drm/i915: gmch: factor out intel_set_memory_cxsr by Imre Deak · 11 years ago
  100. d2011dc drm/i915: Move VLV cmnlane workaround to intel_power_domains_init_hw() by Ville Syrjälä · 11 years ago