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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 8400ab8896324641243b57fc49b448023c07409a / arch / riscv / kernel / entry.S
  1. c677124 Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip by Linus Torvalds · 5 years ago
  2. 556f47a riscv: reject invalid syscalls below -1 by David Abdurachmanov · 5 years ago
  3. 29ff649 sched/rt, riscv: Use CONFIG_PREEMPTION by Thomas Gleixner · 5 years ago
  4. 5ba9aa5 Merge branch 'next/nommu' into for-next by Paul Walmsley · 5 years ago
  5. 6bd33e1 riscv: add nommu support by Christoph Hellwig · 5 years ago
  6. a4c3733 riscv: abstract out CSR names for supervisor vs machine mode by Christoph Hellwig · 5 years ago
  7. 5340627 riscv: add support for SECCOMP and SECCOMP_FILTER by David Abdurachmanov · 5 years ago
  8. cd9e72b8 RISC-V: entry: Remove unneeded need_resched() loop by Valentin Schneider · 5 years ago
  9. 1885660 RISC-V: Clear load reservations while restoring hart contexts by Palmer Dabbelt · 5 years ago
  10. c82dd6d riscv: Avoid interrupts being erroneously enabled in handle_exception() by Vincent Chen · 5 years ago
  11. 4f3f900 riscv: Using CSR numbers to access CSRs by Bin Meng · 5 years ago
  12. 50acfb2 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 by Thomas Gleixner · 6 years ago
  13. a3182c9 RISC-V: Access CSRs using CSR numbers by Anup Patel · 6 years ago
  14. 99fd6e8 RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=y by Vincent Chen · 6 years ago
  15. efe75c4 riscv: add audit support by David Abdurachmanov · 6 years ago
  16. d26c4bb RISC-V: SMP cleanup and new features by Palmer Dabbelt · 6 years ago
  17. 1ed4237 RISC-V: No need to pass scause as arg to do_IRQ() by Anup Patel · 6 years ago
  18. e68ad86 Extract FPU context operations from entry.S by Alan Kao · 6 years ago
  19. 6ea0f26 RISC-V: implement low-level interrupt handling by Christoph Hellwig · 6 years ago
  20. cc6c984 RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler by Palmer Dabbelt · 7 years ago
  21. bcae803 RISC-V: Enable IRQ during exception handling by zongbox@gmail.com · 7 years ago
  22. fe9b842 riscv: disable SUM in the exception handler by Christoph Hellwig · 7 years ago
  23. 1125203 riscv: rename SR_* constants to match the spec by Christoph Hellwig · 7 years ago
  24. 7db91e5 RISC-V: Task implementation by Palmer Dabbelt · 7 years ago