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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 7b2c05a15d29d0570a0d21da1e4fd5cbc85cbf13 / arch / x86 / events / perf_event.h
  1. 7b2c05a perf/x86/intel: Generic support for hardware TopDown metrics by Kan Liang · 4 years, 5 months ago
  2. bbdbde2 perf/x86/intel: Fix the name of perf METRICS by Kan Liang · 4 years, 5 months ago
  3. c085fb8 perf/x86/intel/lbr: Support XSAVES for arch LBR read by Kan Liang · 4 years, 6 months ago
  4. ce711ea perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch by Kan Liang · 4 years, 6 months ago
  5. 47125db perf/x86/intel/lbr: Support Architectural LBR by Kan Liang · 4 years, 6 months ago
  6. fda1f99 perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all() by Kan Liang · 4 years, 6 months ago
  7. 5624986 perf/x86/intel/lbr: Unify the stored format of LBR information by Kan Liang · 4 years, 6 months ago
  8. 49d8184 perf/x86/intel/lbr: Support LBR_CTL by Kan Liang · 4 years, 6 months ago
  9. af6cf12 perf/x86: Expose CPUID enumeration bits for arch LBR by Kan Liang · 4 years, 6 months ago
  10. f42be86 perf/x86/intel/lbr: Use dynamic data structure for task_ctx by Kan Liang · 4 years, 6 months ago
  11. 530bfff perf/x86/intel/lbr: Factor out a new struct for generic optimization by Kan Liang · 4 years, 6 months ago
  12. 799571b perf/x86/intel/lbr: Add the function pointers for LBR save and restore by Kan Liang · 4 years, 6 months ago
  13. c301b1d perf/x86/intel/lbr: Add a function pointer for LBR read by Kan Liang · 4 years, 6 months ago
  14. 9f354a7 perf/x86/intel/lbr: Add a function pointer for LBR reset by Kan Liang · 4 years, 6 months ago
  15. e1ad1ac perf/x86: Keep LBR records unchanged in host context for guest usage by Like Xu · 4 years, 7 months ago
  16. 097e431 perf/x86: Add constraint to create guest LBR event without hw counter by Like Xu · 4 years, 7 months ago
  17. 3cb9d54 perf/x86: Fix variable types for LBR registers by Wei Wang · 4 years, 7 months ago
  18. 3a4ac12 x86/perf: Add hardware performance events support for Zhaoxin CPU. by CodyYao-oc · 4 years, 9 months ago
  19. 5738891 perf/x86/amd: Add support for Large Increment per Cycle Events by Kim Phillips · 5 years ago
  20. 471af00 perf/x86/amd: Constrain Large Increment per Cycle events by Kim Phillips · 5 years ago
  21. 421ca86 perf/x86/intel: Implement LBR callstack context synchronization by Alexey Budankov · 5 years ago
  22. fc1adfe perf/core, perf/x86: Introduce swap_task_ctx() method at 'struct pmu' by Alexey Budankov · 5 years ago
  23. 42880f7 perf/x86/intel: Support PEBS output to PT by Alexander Shishkin · 5 years ago
  24. 552a031 Merge tag 'v5.2' into perf/core, to pick up fixes by Ingo Molnar · 5 years ago
  25. cd6b984 perf/x86: Remove pmu->pebs_no_xmm_regs by Kan Liang · 6 years ago
  26. dce86ac perf/x86: Clean up PEBS_XMM_REGS by Kan Liang · 6 years ago
  27. 6a9f4ef perf/x86: Use update attribute groups for default attributes by Jiri Olsa · 6 years ago
  28. 1f15728 perf/x86: Use update attribute groups for caps by Jiri Olsa · 6 years ago
  29. baa0c83 perf/x86: Use the new pmu::update_attrs attribute group by Jiri Olsa · 6 years ago
  30. 21b0dbc perf/x86: Get rid of x86_pmu::event_attrs by Jiri Olsa · 6 years ago
  31. 6b89d4c perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking by Stephane Eranian · 6 years ago
  32. 6017608 perf/x86/intel: Add Icelake support by Kan Liang · 6 years ago
  33. 63b79f6 perf/x86: Support constraint ranges by Peter Zijlstra · 6 years ago
  34. d3617b98 perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them by Andi Kleen · 6 years ago
  35. c22497f perf/x86/intel: Support adaptive PEBS v4 by Kan Liang · 6 years ago
  36. 878068e perf/x86: Support outputting XMM registers by Kan Liang · 6 years ago
  37. f447e4e perf/x86/intel: Force resched when TFA sysctl is modified by Stephane Eranian · 6 years ago
  38. cc86709 Merge branch 'perf/urgent' into perf/core, to pick up fixes by Ingo Molnar · 6 years ago
  39. 9d5dcc9 perf/x86: Fix incorrect PEBS_REGS by Kan Liang · 6 years ago
  40. 1f6a1e2 perf/x86: Remove PERF_X86_EVENT_COMMITTED by Peter Zijlstra · 6 years ago
  41. f764c58 perf/x86: Fixup typo in stub functions by Peter Zijlstra · 6 years ago
  42. 004cc08 Merge branch 'x86-tsx-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip by Linus Torvalds · 6 years ago
  43. 400816f perf/x86/intel: Implement support for TSX Force Abort by Peter Zijlstra (Intel) · 6 years ago
  44. d01b1f9 perf/x86/intel: Make cpuc allocations consistent by Peter Zijlstra (Intel) · 6 years ago
  45. 9ed8f1a Merge branch 'linus' into perf/core, to pick up fixes by Ingo Molnar · 6 years ago
  46. 81ec3f3 perf/x86: Add check_period PMU callback by Jiri Olsa · 6 years ago
  47. 9b545c0 perf/x86/kvm: Avoid unnecessary work in guest filtering by Andi Kleen · 6 years ago
  48. 67266c1 perf/x86/intel: Add generic branch tracing check to intel_pmu_has_bts() by Jiri Olsa · 6 years ago
  49. af3bdb9 perf/x86/intel: Add a separate Arch Perfmon v4 PMI handler by Andi Kleen · 6 years ago
  50. 3196234 perf/x86/intel: Introduce PMU flag for Extended PEBS by Kan Liang · 7 years ago
  51. 8b077e4a perf/x86/intel/lbr: Optimize context switches for the LBR call stack by Kan Liang · 7 years ago
  52. 0592e57 perf/x86/intel/lbr: Fix incomplete LBR call stack by Kan Liang · 7 years ago
  53. 7054e4e Merge branch 'perf/urgent' into perf/core, to pick up fixes by Ingo Molnar · 7 years ago
  54. 174afc3 perf/x86/intel: Rename confusing 'freerunning PEBS' API and implementation to 'large PEBS' by Kan Liang · 7 years ago
  55. 5bee2cc perf/x86/intel/ds: Introduce ->read() function for auto-reload events and flush the PEBS buffer there by Kan Liang · 7 years ago
  56. bcfbe5c perf/x86: Introduce a ->read() callback in 'struct x86_pmu' by Kan Liang · 7 years ago
  57. f605cfc perf/x86/intel: Fix large period handling on Broadwell CPUs by Kan Liang · 7 years ago
  58. 1197491 x86/events/intel/ds: Add PERF_SAMPLE_PERIOD into PEBS_FREERUNNING_FLAGS by Jiri Olsa · 7 years ago
  59. c1961a4 x86/events/intel/ds: Map debug buffers in cpu_entry_area by Hugh Dickins · 7 years ago
  60. 10043e0 x86/cpu_entry_area: Add debugstore entries to cpu_entry_area by Thomas Gleixner · 7 years ago
  61. 2fe1bc1 perf/x86: Enable free running PEBS for REGS_USER/INTR by Andi Kleen · 7 years ago
  62. fc7ce9c perf/core, x86: Add PERF_SAMPLE_PHYS_ADDR by Kan Liang · 7 years ago
  63. b00233b perf/x86: Export some PMU attributes in caps/ directory by Andi Kleen · 7 years ago
  64. 6ae5fa6 perf/x86: Fix data source decoding for Skylake by Andi Kleen · 7 years ago
  65. 9529835 perf/x86: Move Nehalem PEBS code to flag by Andi Kleen · 7 years ago
  66. dd0b06b perf/x86/intel: Add Goldmont Plus CPU PMU support by Kan Liang · 7 years ago
  67. 6089327 perf/x86: Add sysfs entry to freeze counters on SMI by Kan Liang · 8 years ago
  68. fd583ad perf/x86: Fix spurious NMI with PEBS Load Latency event by Kan Liang · 8 years ago
  69. b0c1ef5 perf/x86: Fix exclusion of BTS and LBR for Goldmont by Andi Kleen · 8 years ago
  70. b800058 perf/x86/intel: Cure bogus unwind from PEBS entries by Peter Zijlstra · 8 years ago
  71. 3e2c1a6 perf/x86/intel: Clean up LBR state tracking by Peter Zijlstra · 8 years ago
  72. 68f7082 perf/x86: Ensure perf_sched_cb_{inc,dec}() is only called from pmu::{add,del}() by Peter Zijlstra · 8 years ago
  73. 09e61b4f perf/x86/intel: Rework the large PEBS setup code by Peter Zijlstra · 8 years ago
  74. 19fc9dd perf/x86/intel: Fix MSR_LAST_BRANCH_FROM_x bug when no TSX by David Carrillo-Cisneros · 9 years ago
  75. fc07e9f perf/x86: Support sysfs files depending on SMT status by Andi Kleen · 9 years ago
  76. ccbebba perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it by Alexander Shishkin · 9 years ago
  77. f21d5ad perf/x86/intel: Add LBR filter support for Silvermont and Airmont CPUs by Kan Liang · 9 years ago
  78. 8b92c3a perf/x86/intel: Add Goldmont CPU support by Kan Liang · 9 years ago
  79. 4c3b73c Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip by Linus Torvalds · 9 years ago
  80. 32b62f4 perf/x86/amd: Cleanup Fam10h NB event constraints by Peter Zijlstra · 9 years ago
  81. a49ac9f perf/x86: Move events_sysfs_show() outside CPU_SUP_INTEL by Huang Rui · 9 years ago
  82. 00f5268 Merge branch 'x86/cleanups' into x86/urgent by Ingo Molnar · 9 years ago
  83. e17dc65 perf/x86/intel: Fix PEBS data source interpretation on Nehalem/Westmere by Andi Kleen · 9 years ago
  84. b3e6246 perf/x86/pebs: Add proper PEBS constraints for Broadwell by Stephane Eranian · 9 years ago
  85. e72daf3 perf/x86/intel: Use PAGE_SIZE for PEBS buffer size on Core2 by Jiri Olsa · 9 years ago
  86. 27f6d22 perf/x86: Move perf_event.h to its new home by Borislav Petkov · 9 years ago[Renamed from arch/x86/kernel/cpu/perf_event.h]
  87. 1e7b939 perf/x86/intel: Add perf core PMU support for Intel Knights Landing by Harish Chegondi · 9 years ago
  88. 7246976 perf/x86: Use INST_RETIRED.PREC_DIST for cycles: ppp by Andi Kleen · 9 years ago
  89. f1ad448 perf/x86: Remove old MSR perf tracing code by Andi Kleen · 9 years ago
  90. 42a0789 Merge branch 'perf/urgent' into perf/core, to pick up fixes by Ingo Molnar · 9 years ago
  91. 169b932 perf/x86/intel: Fix INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA macro by Jiri Olsa · 9 years ago
  92. b7883a1 perf/x86: Handle multiple umask bits for BDW CYCLE_ACTIVITY.* by Andi Kleen · 9 years ago
  93. 90eec10 treewide: Remove old email address by Peter Zijlstra · 9 years ago
  94. b28ae95 perf/x86: Fix LBR call stack save/restore by Andi Kleen · 9 years ago
  95. 02386c3 Merge branch 'perf/urgent' into perf/core, to pick up fixes before applying new changes by Ingo Molnar · 9 years ago
  96. d0dc849 perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake by Andi Kleen · 9 years ago
  97. 8f3e568 perf/core: Drop PERF_EVENT_TXN by Sukadev Bhattiprolu · 9 years ago
  98. fbbe070 perf/core: Add a 'flags' parameter to the PMU transactional interfaces by Sukadev Bhattiprolu · 9 years ago
  99. 47732d8 perf/x86: Make merge_attr() global to use from perf_event_intel by Andi Kleen · 10 years ago
  100. 9a92e16 perf/x86/intel: Add Intel Skylake PMU support by Andi Kleen · 10 years ago