1. 1802d0b treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 by Thomas Gleixner · 6 years ago
  2. 082ce27 irqchip/bcm: Restore registration print with %pOF by Florian Fainelli · 6 years ago
  3. dc3173c irqchip/brcmstb-l2: Make two init functions static by YueHaibing · 6 years ago
  4. 3351788 irqchip/brcmstb-l2: Use _irqsave locking variants in non-interrupt code by Doug Berger · 6 years ago
  5. 2d02424 irqchip/bcm: Remove hashed address printing by Jaedon Shin · 7 years ago
  6. c0ca726 irqchip/brcmstb-l2: Add support for the BCM7271 L2 controller by Doug Berger · 7 years ago
  7. 8480ca4 irqchip/brcmstb-l2: Abstract register accesses by Doug Berger · 7 years ago
  8. 49aa6ef irqchip/brcmstb-l2: Remove some processing from the handler by Doug Berger · 7 years ago
  9. c017d21 irqchip: brcmstb-l2: Define an irq_pm_shutdown function by Florian Fainelli · 7 years ago
  10. 97139d4 treewide: remove redundant #include <linux/kconfig.h> by Masahiro Yamada · 8 years ago
  11. 2ae9add irqchip/brcmstb-l2: Make of probe function static by Ben Dooks · 9 years ago
  12. bd0b9ac genirq: Remove irq argument from irq flow handlers by Thomas Gleixner · 9 years ago
  13. 00db2ae irqchip/brcmstb-l2: Prepare brcmstb_l2_intc_irq_handle for irq argument removal by Thomas Gleixner · 9 years ago
  14. f286c17 irqchip/brcmstb-l2: Consolidate chained IRQ handler install/remove by Thomas Gleixner · 10 years ago
  15. 41a83e06 irqchip: Prepare for local stub header removal by Joel Porquet · 10 years ago
  16. c9ae71e IRQCHIP: brcmstb-l2: don't clear wakeable interrupts at init time by Brian Norris · 10 years ago
  17. ecb50f0 Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip by Linus Torvalds · 10 years ago
  18. d99ba44 irqchip: brcmstb-l2: Fix error handling of irq_of_parse_and_map by Dmitry Torokhov · 10 years ago
  19. 1abbdba irqchip: brcmstb-l2: Convert driver to use irq_reg_{readl,writel} by Kevin Cernekee · 10 years ago
  20. 05f1275 irqchip: brcmstb-l2: Eliminate dependency on ARM code by Kevin Cernekee · 10 years ago
  21. 00ac202 irqchip: brcmstb-l2: Level-2 interrupts are edge sensitive by Florian Fainelli · 11 years ago
  22. 7f646e9 irqchip: brcmstb-l2: Add Broadcom Set Top Box Level-2 interrupt controller by Florian Fainelli · 11 years ago