Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 710c476514313c74045c41c0571bb5178fd16e3d / arch / riscv / kernel / head.S
  1. 2ffc48f RISC-V: Move spinwait booting method to its own config by Atish Patra · 3 years ago
  2. 0b39eb3 RISC-V: Move the entire hart selection via lottery to SMP by Atish Patra · 3 years ago
  3. c78f94f RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method by Atish Patra · 3 years ago
  4. 9a2451f RISC-V: Avoid using per cpu array for ordered booting by Atish Patra · 3 years ago
  5. 0c34e79 RISC-V: Introduce sv48 support without relocatable kernel by Palmer Dabbelt · 3 years ago
  6. e8a62cc riscv: Implement sv48 support by Alexandre Ghiti · 3 years, 1 month ago
  7. 51f23e5 riscv: head: remove useless __PAGE_ALIGNED_BSS and .balign by Jisheng Zhang · 3 years, 1 month ago
  8. 153c46f riscv: head: make secondary_start_common() static by Jisheng Zhang · 3 years, 1 month ago
  9. 8ee3043 riscv/head: fix misspelling of guaranteed by hasheddan · 3 years, 1 month ago
  10. b89f311 Merge tag 'riscv-for-linus-5.16-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux by Linus Torvalds · 3 years, 1 month ago
  11. 0146337 Merge tag 'cpu-to-thread_info-v5.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux by Linus Torvalds · 3 years, 2 months ago
  12. 64a1959 riscv: fix misalgned trap vector base address by Chen Lu · 3 years, 2 months ago
  13. f9ace4e riscv: remove .text section size limitation for XIP by Vitaly Wool · 3 years, 3 months ago
  14. 8aa0fb0 riscv: rely on core code to keep thread_info::cpu updated by Ard Biesheuvel · 3 years, 3 months ago
  15. 658e2c5 riscv: Introduce structure that group all variables regarding kernel mapping by Alexandre Ghiti · 3 years, 6 months ago
  16. 44c9225 RISC-V: enable XIP by Vitaly Wool · 3 years, 9 months ago
  17. 2bfc6cd riscv: Move kernel mapping outside of linear mapping by Alexandre Ghiti · 3 years, 9 months ago
  18. f105aa9 riscv: add BUILTIN_DTB support for MMU-enabled targets by Vitaly Wool · 4 years ago
  19. e2ae634 Merge tag 'riscv-for-linus-5.11-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux by Linus Torvalds · 4 years ago
  20. 5cb0080 riscv: Enable ARCH_STACKWALK by Kefeng Wang · 4 years, 1 month ago
  21. 79605f1 riscv: Set text_offset correctly for M-Mode by Sean Anderson · 4 years, 2 months ago
  22. cb7d2dd RISC-V: Add PE/COFF header for EFI stub by Atish Patra · 4 years, 3 months ago
  23. 8f3a2b4 RISC-V: Move DT mapping outof fixmap by Anup Patel · 4 years, 3 months ago
  24. 54701a0 RISC-V: Fix duplicate included thread_info.h by Tian Tao · 4 years, 3 months ago
  25. 76d4467 riscv: Setup exception vector for nommu platform by Qiu Wenbo · 4 years, 5 months ago
  26. 79b1feb RISC-V: Setup exception vector early by Atish Patra · 4 years, 5 months ago
  27. eb077c9 RISC-V: Skip setting up PMPs on traps by Palmer Dabbelt · 4 years, 9 months ago
  28. 335b139 riscv: Add SOC early init support by Damien Le Moal · 4 years, 10 months ago
  29. cfafe26 RISC-V: Add supported for ordered booting method using HSM by Atish Patra · 4 years, 9 months ago
  30. e011995 RISC-V: Move relocate and few other functions out of __init by Atish Patra · 4 years, 9 months ago
  31. c68a903 riscv: set pmp configuration if kernel is running in M-mode by Greentime Hu · 5 years ago
  32. 8ad8b72 riscv: Add KASAN support by Nick Hu · 5 years ago
  33. 20d2292 riscv: make sure the cores stay looping in .Lsecondary_park by Greentime Hu · 5 years ago
  34. dc6fcba riscv: Fixup obvious bug for fp-regs reset by Guo Ren · 5 years ago
  35. d411cf0 riscv: fix scratch register clearing in M-mode. by Greentime Hu · 5 years ago
  36. 6bd33e1 riscv: add nommu support by Christoph Hellwig · 5 years ago
  37. 9e80635 riscv: clear the instruction cache and all registers when booting by Christoph Hellwig · 5 years ago
  38. accb9db riscv: read the hart ID from mhartid on boot by Damien Le Moal · 5 years ago
  39. a4c3733 riscv: abstract out CSR names for supervisor vs machine mode by Christoph Hellwig · 5 years ago
  40. b47613d arch/riscv: disable excess harts before picking main boot hart by Xiang Wang · 5 years ago
  41. 58d4faf Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux by Linus Torvalds · 5 years ago
  42. 474efec riscv: modify the Image header to improve compatibility with the ARM64 header by Paul Walmsley · 5 years ago
  43. 4f3f900 riscv: Using CSR numbers to access CSRs by Bin Meng · 5 years ago
  44. 0f327f2 RISC-V: Add an Image header that boot loader can parse. by Atish Patra · 6 years ago
  45. 671f9a3 RISC-V: Setup initial page tables in two stages by Anup Patel · 6 years ago
  46. 50acfb2 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 by Thomas Gleixner · 6 years ago
  47. 4c3aeb8 RISC-V: Avoid using invalid intermediate translations by Palmer Dabbelt · 6 years ago
  48. a3182c9 RISC-V: Access CSRs using CSR numbers by Anup Patel · 6 years ago
  49. ba9c014 riscv: cleanup the parse_dtb calling conventions by Christoph Hellwig · 6 years ago
  50. c637b91 riscv: simplify the stack pointer setup in head.S by Christoph Hellwig · 6 years ago
  51. df16c40 riscv: clear all pending interrupts when booting by Christoph Hellwig · 6 years ago
  52. c0fbcd9 RISC-V: Build flat and compressed kernel images by Anup Patel · 6 years ago
  53. f99fb60 RISC-V: Use Linux logical CPU number instead of hartid by Atish Patra · 6 years ago
  54. 94f592f RISC-V: Add the directive for alignment of stvec's value by Zong Li · 6 years ago
  55. 8b08f50 Rename sbi_save to parse_dtb to improve code readability by Michael Clark · 7 years ago
  56. 7549cdf riscv: rename sptbr to satp by Christoph Hellwig · 7 years ago
  57. 83e7b87 RISC-V: move empty_zero_page definition to C and export it by Olof Johansson · 7 years ago
  58. 76d2a04 RISC-V: Init and Halt Code by Palmer Dabbelt · 7 years ago