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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 506dfc9906e5cbf453bbcd5eb627689435583558 / drivers / clk / mediatek / clk-pll.c
  1. 1802d0b treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 by Thomas Gleixner · 6 years ago
  2. dac5d67 clk: mediatek: Allow changing PLL rate when it is off by James Liao · 6 years ago
  3. 23fe31d clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data by Weiyi Lu · 6 years ago
  4. 9d7e1a8 clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data by Owen Chen · 6 years ago
  5. be17ca6 clk: mediatek: Disable tuner_en before change PLL rate by Owen Chen · 6 years ago
  6. c955bf3 clk: mediatek: add the option for determining PLL source clock by Chen Zhong · 7 years ago
  7. e2f744a clk: mediatek: Add MT2712 clock support by weiyi.lu@mediatek.com · 7 years ago
  8. e986211 clk: mediatek: Add MT2701 clock support by Shunli Wang · 8 years ago
  9. 928f3bf clk: mediatek: remove __init from clk registration functions by James Liao · 8 years ago
  10. cdb2bab clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS by James Liao · 10 years ago
  11. 75ce0cd clk: mediatek: Add MT8173 MMPLL change rate support by James Liao · 9 years ago
  12. 196de71 clk: mediatek: Fix calculation of PLL rate settings by James Liao · 9 years ago
  13. b3be457 clk: mediatek: Fix PLL registers setting flow by James Liao · 9 years ago
  14. 95f5898 clk: mediatek: Initialize clk_init_data by Ricky Liang · 10 years ago
  15. 9741b1a clk: mediatek: Add initial common clock support for Mediatek SoCs. by James Liao · 10 years ago