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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 4da46e1e5bb7e7396fad172cdaffbe496562f3d8 / drivers / gpu / drm / i915 / i915_reg.h
  1. 4da46e1 drm/i915/bdw: GEN-specific logical ring emit request by Oscar Mateo · 10 years ago
  2. 8670d6f drm/i915/bdw: Populate LR contexts (somewhat) by Oscar Mateo · 10 years ago
  3. 01e184c drm/i915: Add sprite watermark programming for VLV and CHV by Gajanan Bhat · 10 years ago
  4. 0948c26 drm/i915: Generalize drain latency computation by Gajanan Bhat · 10 years ago
  5. efd814b drm/i915: Polish the chv cmnlane resrt macros by Ville Syrjälä · 11 years ago
  6. 1abc4dc drm/i915: Parametrize VLV_DDL registers by Ville Syrjälä · 11 years ago
  7. 0a56067 drm/i915: Fill out the FWx watermark register defines by Ville Syrjälä · 11 years ago
  8. 76eebda drm/i915: Add 180 degree sprite rotation support by Ville Syrjälä · 10 years ago
  9. 7fad359 drm/i915: remove duplicate register defines by Paulo Zanoni · 10 years ago
  10. da46f93 drm/i915: Introduce FBC False Color for debug purposes. by Rodrigo Vivi · 10 years ago
  11. 1fb4450 drm/i915: Clarify CHV swing margin/deemph bits by Ville Syrjälä · 11 years ago
  12. 383c5a6 drm/i915: Add cdclk change support for chv by Ville Syrjälä · 11 years ago
  13. aad3d14 drm/i915: Add DP training pattern 3 for CHV by Ville Syrjälä · 11 years ago
  14. 2ce147f drm/i915: Add chv port D TX wells by Ville Syrjälä · 11 years ago
  15. 26972b0 drm/i915: Add per-pipe power wells for chv by Ville Syrjälä · 11 years ago
  16. 5d6f7ea drm/i915: Add chv cmnlane power wells by Ville Syrjälä · 11 years ago
  17. 22c5aee drm/i915: Fix drain latency precision multipler for VLV by Zhenyu Wang · 11 years ago
  18. 5d42f82 Merge tag 'v3.16' into drm-next by Dave Airlie · 10 years ago
  19. 4dac3ed Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next by Daniel Vetter · 10 years ago
  20. 01b887c drm/i915: add some registers need for displayport MST support. by Dave Airlie · 11 years ago
  21. 542a6b2 drm/i915/chv: calculate rc6 residency correctly by Mika Kuoppala · 11 years ago
  22. 67c3bf6 drm/i915: populate mem_freq/cz_clock for chv by Deepak S · 11 years ago
  23. 716c2e5 drm/i915: Switch to common shared dpll framework for WRPLLs by Daniel Vetter · 11 years ago
  24. d452c5b drm/i915: State readout support for WRPLLs by Daniel Vetter · 11 years ago
  25. 26804af drm/i915: State readout and cross-checking for ddi_pll_sel by Daniel Vetter · 11 years ago
  26. 114fe48 drm/i915: Clean up WRPLL/SPLL #defines by Daniel Vetter · 11 years ago
  27. 9ccd5ae drm/i915: fix D_COMP usage on BDW by Paulo Zanoni · 11 years ago
  28. f1e1c21 drm/i915: Don't clobber the GTT when it's within stolen memory by Ville Syrjälä · 11 years ago
  29. 31685c2 drm/i915/vlv: WA for Turbo and RC6 to work together. by Deepak S · 11 years ago
  30. 5ee426c drm/i915/bdw: implement semaphore wait by Ben Widawsky · 11 years ago
  31. 3e78998 drm/i915/bdw: implement semaphore signal by Ben Widawsky · 11 years ago
  32. 9cf33db drm/i915: Give names to the CCK_DISPLAY_CLOCK_CONTROL bits by Ville Syrjälä · 11 years ago
  33. c9224fa drm/i915: Add some L3 registers to the parser whitelist by Brad Volkin · 11 years ago
  34. 9576c27 drm/i915: update BDW DDI buffer translations by Paulo Zanoni · 11 years ago
  35. 82c5625 drm/i915: BDW PSR: Add single frame update support. by Rodrigo Vivi · 11 years ago
  36. a8aab8b drm/i915: Fix VLV CRC reading. by Rodrigo Vivi · 11 years ago
  37. a211b49 drm/i915: Add #defines for short/long pulse on gmch platforms by Daniel Vetter · 11 years ago
  38. a2560a6 drm/i915: Use transcoder as index to MIPI regs by Shashank Sharma · 11 years ago
  39. 4ad83e9 drm/i915: Change Mipi register definitions by Shashank Sharma · 11 years ago
  40. 2dcbc34 drm/i915/chv: Handle video DIP registers on CHV by Ville Syrjälä · 11 years ago
  41. 2d401b1 drm/i915: Don't use pipe_offset stuff for DPLL registers by Ville Syrjälä · 11 years ago
  42. b9e5ac3 drm/i915/chv: Force clock buffer enables by Ville Syrjälä · 11 years ago
  43. 9197c88 drm/i915/chv: Try to program the PHY used clock channel overrides by Ville Syrjälä · 11 years ago
  44. 2b6b3a0 drm/i915/chv: Enable RPS (Turbo) for Cherryview by Deepak S · 11 years ago
  45. 3880774 drm/i915/chv: Enable Render Standby (RC6) for Cherryview by Deepak S · 11 years ago
  46. 54e472a drm/i915: Enable interrupt-based AGPBUSY# enable on 85x by Ville Syrjälä · 11 years ago
  47. 3299254 drm/i915: Flip the sense of AGPBUSY_DIS bit by Ville Syrjälä · 11 years ago
  48. fa4f53c drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk by Ville Syrjälä · 11 years ago
  49. 0e76718 drm/i915: Add a brief description of the VLV display PHY internals by Ville Syrjälä · 11 years ago
  50. 75f7f3e drm/i915: Fix mmio vs. CS flip race on ILK+ by Ville Syrjälä · 11 years ago
  51. 646b426 drm/i915: Drop /** */ comments from i915_reg.h by Ville Syrjälä · 11 years ago
  52. e4443e4 drm/i915/chv: Add a bunch of pre production workarounds by Ville Syrjälä · 11 years ago
  53. 1966e59 drm/i915/chv: Use RMW to toggle swing calc init by Ville Syrjälä · 11 years ago
  54. f72df8d drm/i915/chv: Don't do group access reads from TX lanes either by Ville Syrjälä · 11 years ago
  55. 97fd4d5 drm/i915/chv: Don't use PCS group access reads by Ville Syrjälä · 11 years ago
  56. d2152b2 drm/i915/chv: Set soft reset override bit for data lane resets by Ville Syrjälä · 11 years ago
  57. 9418c1f drm/i915/chv: Register port D encoders and connectors by Ville Syrjälä · 11 years ago
  58. 71485e0 drm/i915/chv: Fix PORT_TO_PIPE for CHV by Ville Syrjälä · 11 years ago
  59. 5efb3e2 drm/i915/chv: Add cursor pipe offsets by Ville Syrjälä · 11 years ago
  60. c0c3532 drm/i915/chv: Fix gmbus for port D by Ville Syrjälä · 11 years ago
  61. 84fd4f4 drm/i915/chv: Add CHV display support by Rafael Barbalho · 11 years ago
  62. b3a3f03 drm/i915: Fix ILK GPU reset domain bits by Ville Syrjälä · 11 years ago
  63. b6fdd0f drm/i915: Add MIPI mmio reg base by Shashank Sharma · 11 years ago
  64. cf63e4a drm/i915: rename IOSF sideband opcodes according to the spec by Imre Deak · 11 years ago
  65. baccd45 drm/i915: Enable PM Interrupts target via Display Interface. by Deepak S · 11 years ago
  66. 0961021 drm/i915/bdw: Implement a basic PM interrupt handler by Ben Widawsky · 11 years ago
  67. 44f37d1 drm/i915/chv: Pipe select change for DP and HDMI by Chon Ming Lee · 11 years ago
  68. 9d556c9 drm/i915/chv: Add update and enable pll for Cherryview by Chon Ming Lee · 11 years ago
  69. 076ed3b drm/i915/chv: Trigger phy common lane reset by Chon Ming Lee · 11 years ago
  70. 00fc31b drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2 by Chon Ming Lee · 11 years ago
  71. a09cadd drm/i915/chv: Add DPIO offset for Cherryview. v3 by Chon Ming Lee · 11 years ago
  72. c294c54 drm/i915/chv: Add DDL register defines for Cherryview by Ville Syrjälä · 11 years ago
  73. 9e72b46 drm/i915: add various missing GTI/Gunit register definitions by Imre Deak · 11 years ago
  74. bf67a6f drm/i915/chv: Add DPINVGTT registers defines for Cherryview by Ville Syrjälä · 11 years ago
  75. fac12f6 drm/i915/chv: Add display interrupt registers bits for Cherryview by Ville Syrjälä · 11 years ago
  76. f3c67fd drm/i915/chv: Add DPFLIPSTAT register bits for Cherryview by Ville Syrjälä · 11 years ago
  77. 8cc96e7 drm/i915/chv: Add PIPESTAT register bits for Cherryview by Ville Syrjälä · 11 years ago
  78. 9cc19be drm/i915: vlv: add RC6 residency counters by Imre Deak · 11 years ago
  79. 981a5ae drm/i915: vlv: clean up GTLC wake control/status register macros by Imre Deak · 11 years ago
  80. 845f74a drm/i915:Initialize the second BSD ring on BDW GT3 machine by Zhao Yakui · 11 years ago
  81. 439d7ac drm/i915: Add support for DRRS to switch RR by Pradeep Bhat · 11 years ago
  82. 113a047 drm/i915: Add more registers to the whitelist for mesa by Brad Volkin · 11 years ago
  83. d0e1f1c drm/i915: Rename GEN8_PIPE_FLIP_DONE to PRIMARY_FLIP_DONE by Damien Lespiau · 11 years ago
  84. b76bfeb drm/i915/bdw: Provide a gen8 version of SRM by Damien Lespiau · 11 years ago
  85. 7ec55f4 drm/i915: Protect the argument expansion in LRI and SRM macros by Damien Lespiau · 11 years ago
  86. 4e04632 drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush' by Akash Goel · 11 years ago
  87. 9991ae7 drm/i915: Move all ring resets before setting the HWS page by Chris Wilson · 11 years ago
  88. eb6008a drm/i915: Fix framecount offset by Rafael Barbalho · 11 years ago
  89. 13ffadd drm/i915/bdw: Expand FADD to 64bit by Ben Widawsky · 11 years ago
  90. 180b813 drm/i915: Add OACONTROL to the command parser register whitelist. by Kenneth Graunke · 11 years ago
  91. 114d4f7 drm/i915: Reject commands that would store to global HWS page by Brad Volkin · 11 years ago
  92. d4d4803 drm/i915: Enable PPGTT command parser checks by Brad Volkin · 11 years ago
  93. b18b396 drm/i915: Reject commands that explicitly generate interrupts by Brad Volkin · 11 years ago
  94. f0a346b drm/i915: Enable register whitelist checks by Brad Volkin · 11 years ago
  95. 220375a drm/i915: Add register whitelist for DRM master by Brad Volkin · 11 years ago
  96. 5947de9 drm/i915: Add register whitelists for mesa by Brad Volkin · 11 years ago
  97. 9c640d1 drm/i915: Reject privileged commands by Brad Volkin · 11 years ago
  98. 3a6fa98 drm/i915: Initial command parser table definitions by Brad Volkin · 11 years ago
  99. a028c4b drm/i915: Add FIXME for bdw semaphore detection in hancheck by Daniel Vetter · 11 years ago
  100. aa83e30 drm/i915: Rename GFX_TLB_INVALIDATE_ALWAYS by Chris Wilson · 11 years ago