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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 3eb616b26408ac813c67280cf883f36d98b8441d / drivers / clk / tegra / clk-pll.c
  1. 7808638 clk: tegra: Don't allow zero clock rate for PLLs by Dmitry Osipenko · 3 years, 8 months ago
  2. a719604 clk: tegra: Ensure that PLLU configuration is applied properly by Dmitry Osipenko · 3 years, 8 months ago
  3. 0c7ea2b clk: tegra: Don't enable PLLE HW sequencer at init by JC Kuo · 4 years ago
  4. 5105660 clk: tegra: Always program PLL_E when enabled by Thierry Reding · 4 years, 8 months ago
  5. 6402e780 clk: tegra: Capitalization fixes by Thierry Reding · 4 years, 8 months ago
  6. fa64023 clk: tegra: pll: Improve PLLM enable-state detection by Dmitry Osipenko · 4 years, 6 months ago
  7. 9157abe clk: tegra: pll: Add pre/post rate-change hooks by Dmitry Osipenko · 4 years, 10 months ago
  8. bc0b3a6 clk: tegra: pll: Save and restore pll context by Sowjanya Komatineni · 5 years ago
  9. 9952f69 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 by Thomas Gleixner · 6 years ago
  10. 40db569 clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider by Dmitry Osipenko · 6 years ago
  11. bff1cef clk: tegra: Don't enable already enabled PLLs by Dmitry Osipenko · 6 years ago
  12. 08441a96 clk: tegra: Return the exact clock rate from clk_round_rate by Robert Yang · 6 years ago
  13. c35b518 clk: tegra: Fix pll_u rate configuration by Marcel Ziswiler · 7 years ago
  14. 2f924ac clk: tegra: Fix T210 PLLRE registration by Alex Frid · 7 years ago
  15. f7bdb8b clk: tegra: Update T210 PLLSS (D2/DP) registration by Alex Frid · 7 years ago
  16. ac99afe clk: tegra: Re-factor T210 PLLX registration by Alex Frid · 7 years ago
  17. 3dd065e clk: tegra: change post IDDQ release delay to 5us by Peter De Schrijver · 7 years ago
  18. bc7b34a clk: tegra: Init cfg structure in _get_pll_mnp by Peter De Schrijver · 7 years ago
  19. 04434cf clk: tegra: Enable PLL_SS for Tegra210 by Peter De Schrijver · 7 years ago
  20. 1a7da87 clk: tegra: fix SS control on PLL enable/disable by Peter De Schrijver · 7 years ago
  21. e745f99 clk: tegra: Rework pll_u by Peter De Schrijver · 8 years ago
  22. 15d68e8 clk: tegra: Initialize UTMI PLL when enabling PLLU by Andrew Bresticker · 9 years ago
  23. 926655f clk: tegra: Fix pllre Tegra210 and add pll_re_out1 by Rhyland Klein · 9 years ago
  24. 442f53f clk: tegra: Fix PLLE SS coefficients by Mark Kuo · 9 years ago
  25. fd2963b clk: tegra: Fix typos around clearing PLLE bits during enable by Rhyland Klein · 9 years ago
  26. f59b016 clk: tegra: Do not disable PLLE when under hardware control by Mark Kuo · 9 years ago
  27. 3eb6156 clk: tegra: pll: Fix potential sleeping-while-atomic by Andrew Bresticker · 9 years ago
  28. 2d7f61f3 clk: tegra: Read correct IDDQ register in PLL_SS registration by Bill Huang · 10 years ago
  29. a4ca2b2 clk: tegra: Fix WARN_ON in PLL_RE registration by Bill Huang · 10 years ago
  30. afff455 clk: tegra: pll: Fix issues with rates for VCO PLLs by Andrew Bresticker · 10 years ago
  31. 6b301a0 clk: tegra: Add support for Tegra210 clocks by Rhyland Klein · 10 years ago
  32. 0ef9db6 clk: tegra: pll: Add logic for SS by Bill Huang · 10 years ago
  33. 17e9273 clk: tegra: pll: Add dyn_ramp callback by Rhyland Klein · 10 years ago
  34. b985114 clk: tegra: pll: Add Set_default logic by Bill Huang · 10 years ago
  35. b5512b4 clk: tegra: pll: Adjust vco_min if SDM present by Bill Huang · 10 years ago
  36. 6929715 clk: tegra: pll: Add support for PLLMB for Tegra210 by Rhyland Klein · 10 years ago
  37. dd322f0 clk: tegra: pll: Add specialized logic for Tegra210 by Rhyland Klein · 10 years ago
  38. 267b62a clk: tegra: pll: Update PLLM handling by Danny Huang · 10 years ago
  39. 86c679a clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate by Rhyland Klein · 10 years ago
  40. fde207e clk: tegra: pll: Add code to handle if resets are supported by PLL by Bill Huang · 10 years ago
  41. 407254d clk: tegra: pll: Add logic for out-of-table rates for T210 by Rhyland Klein · 10 years ago
  42. d907f4b clk: tegra: pll: Add logic for handling SDM data by Rhyland Klein · 10 years ago
  43. 3706b43 clk: tegra: pll: Don't unconditionally set LOCK flags by Rhyland Klein · 10 years ago
  44. 204c85d clk: tegra: pll: Update warning message by Rhyland Klein · 10 years ago
  45. 7db864c clk: tegra: pll: Simplify clk_enable_path by Rhyland Klein · 10 years ago
  46. 6583a63 clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header by Rhyland Klein · 10 years ago
  47. 385f9ad clk: tegra: Constify pdiv-to-hw mappings by Thierry Reding · 9 years ago
  48. e52d7c0 clk: tegra: Miscellaneous coding style cleanups by Thierry Reding · 9 years ago
  49. 836ee0f clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw) by Stephen Boyd · 9 years ago
  50. 5cdb1dc clk: tegra: Convert to clk_hw based provider APIs by Stephen Boyd · 9 years ago
  51. 584ac4e clk: tegra: Properly include clk.h by Stephen Boyd · 10 years ago
  52. 44a6f3db clk: tegra: Remove needless initializations by Thierry Reding · 10 years ago
  53. 6bb18c5 clk: tegra: Various whitespace cleanups by Thierry Reding · 10 years ago
  54. 08acae3 clk: tegra: Add support for the Tegra132 CAR IP block by Paul Walmsley · 10 years ago
  55. ca036b2 clk: tegra: Fix order of arguments in WARN by Tomeu Vizoso · 10 years ago
  56. 0e548d50b clk: tegra: Use XUSB-compatible SATA PLL sequence by Mikko Perttunen · 11 years ago
  57. 37ab366 clk: tegra: Enable hardware control of SATA PLL by Mikko Perttunen · 11 years ago
  58. 4c8f806 Merge branch 'clk-fixes' into clk-next by Mike Turquette · 11 years ago
  59. 51784380 Merge tag 'clk-tegra-fixes-3.15' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes by Mike Turquette · 11 years ago
  60. 2cfe167 clk: tegra: Enable hardware control of PLLE by Jim Lin · 11 years ago
  61. d2c834a clk: tegra: Fix wrong value written to PLLE_AUX by Tuomas Tynkkynen · 11 years ago
  62. 4ccc402 clk: tegra: Fix enabling of PLLE by Thierry Reding · 11 years ago
  63. c61e4e7 clk: tegra: Introduce divider mask and shift helpers by Thierry Reding · 11 years ago
  64. d0f02ce clk: tegra: Fix PLLE programming by Thierry Reding · 11 years ago
  65. e47e12f clk: tegra: Staticize local variables in clk-pll.c by Sachin Kamat · 11 years ago
  66. 62ce7cd clk: tegra: fix __clk_lookup() return value checks by Wei Yongjun · 11 years ago
  67. 8ba4b3b clk: tegra: Do not print errors for clk_round_rate() by Thierry Reding · 11 years ago
  68. 798e910 clk: tegra: Add support for PLLSS by Peter De Schrijver · 11 years ago
  69. ebe142b clk: tegra: move fields to tegra_clk_pll_params by Peter De Schrijver · 11 years ago
  70. 8e9cc80 clk: tegra: use pll_ref as the pll_e parent by Peter De Schrijver · 11 years ago
  71. 04edb09 clk: tegra: move some PLLC and PLLXC init to clk-pll.c by Peter De Schrijver · 11 years ago
  72. 00c674e clk: tegra: Fix clock rate computation by Thierry Reding · 11 years ago
  73. 642fb0c clk: tegra: PLLE spread spectrum control by Peter De Schrijver · 11 years ago
  74. 408a24f clk: tegra: Use override bits when needed by Peter De Schrijver · 12 years ago
  75. 35d287a clk: tegra: fix pllre initilization by Peter De Schrijver · 12 years ago
  76. aa6fefd clk: tegra: allow PLL m,n,p init from SoC files by Peter De Schrijver · 12 years ago
  77. 053b525 clk: tegra: pllc and pllxc should use pdiv_map by Peter De Schrijver · 12 years ago
  78. c1d1939 clk: tegra: Add new fields and PLL types for Tegra114 by Peter De Schrijver · 12 years ago
  79. 3e72771 clk: tegra: move from a lock bit idx to a lock mask by Peter De Schrijver · 12 years ago
  80. 0b6525a clk: tegra: Add PLL post divider table by Peter De Schrijver · 12 years ago
  81. 7ba2881 clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE by Peter De Schrijver · 12 years ago
  82. dd93587 clk: tegra: Add TEGRA_PLL_BYPASS flag by Peter De Schrijver · 12 years ago
  83. dba4072 clk: tegra: Refactor PLL programming code by Peter De Schrijver · 12 years ago
  84. 8f8f484 clk: tegra: add Tegra specific clocks by Prashant Gaikwad · 12 years ago