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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 2837ac40698d0931727b957a40c8c8ea27c3bcb2 / drivers / gpu / drm / i915 / intel_pm.c
  1. 2837ac4 drm/i915: vlv: increase timeout when setting idle GPU freq by Imre Deak · 10 years ago
  2. 6985b35 drm/i915: Update ring freq for full gpu freq range by Tom O'Rourke · 10 years ago
  3. c7f3153 drm/i915: change initial rps frequency for gen8 by Tom O'Rourke · 10 years ago
  4. f4ab408 drm/i915: Keep min freq above floor on HSW/BDW by Tom O'Rourke · 10 years ago
  5. 93ee292 drm/i915: Use efficient frequency for HSW/BDW by Tom O'Rourke · 10 years ago
  6. 54499b2 Merge tag 'drm-intel-fixes-2014-11-19' into drm-intel-next-queued by Daniel Vetter · 10 years ago
  7. 2eb5252 drm/i915: disable rps irqs earlier during suspend/unload by Imre Deak · 10 years ago
  8. d4d70aa drm/i915: sanitize rps irq disabling by Imre Deak · 10 years ago
  9. 3cc134e drm/i915: sanitize rps irq enabling by Imre Deak · 10 years ago
  10. e534770 drm/i915: move rps irq disable one level up by Imre Deak · 10 years ago
  11. 151a49d drm/i915: Extend pcode mailbox interface by Tom O'Rourke · 10 years ago
  12. ab3fb15 drm/i915: Change CHV SKU400 GPU freq divider to 10 by Ville Syrjälä · 10 years ago
  13. 80b83b6 drm/i915: Add missing newline to 'DDR speed' debug messages by Ville Syrjälä · 10 years ago
  14. dd06f88 drm/i915: Refactor vlv/chv GPU frequency divider setup by Ville Syrjälä · 10 years ago
  15. ce611ef drm/i915: Improve PCBR debug information by Ville Syrjälä · 10 years ago
  16. 8d40c3a drm/i915: Warn if GPLL isn't used on vlv/chv by Ville Syrjälä · 10 years ago
  17. c8e9627 drm/i915: Add a name for the Punit GPLLENABLE bit by Ville Syrjälä · 10 years ago
  18. 9a3b9c7 drm/i915: Silence valleyview_set_rps() by Ville Syrjälä · 10 years ago
  19. 2208d65 drm/i915: drop WaSetupGtModeTdRowDispatch:snb by Daniel Vetter · 10 years ago
  20. f5ed50c drm/i915: Let's hope future platforms will use the same WM code as SKL by Damien Lespiau · 10 years ago
  21. dddab34 drm/i915: Clear PCODE_DATA1 on SNB+ by Damien Lespiau · 10 years ago
  22. c6e8f39 drm/i915: Read the CCK fuse register from CCK by Ville Syrjälä · 10 years ago
  23. b900b94 drm/i915: move rps irq enable/disable to i915_irq.c by Imre Deak · 10 years ago
  24. 20415c5 drm/i915: unify gen6/gen8 rps irq enable/disable by Imre Deak · 10 years ago
  25. a72fbc3 drm/i915: unify gen6/gen8 pm irq helpers by Imre Deak · 10 years ago
  26. 3e470ea drm/i915/chv: Remove pre-production workarounds by Arun Siluvery · 10 years ago
  27. 20e4936 drm/i915/skl: Enable Gen9 RC6 by Zhe Wang · 10 years ago
  28. d21b795 drm/i915/skl: Log the order in which we flush the pipes in the WM code by Damien Lespiau · 10 years ago
  29. 0e8fb7b drm/i915/skl: Flush the WM configuration by Damien Lespiau · 10 years ago
  30. 34bb56a drm/i915/skl: Stage the pipe DDB allocation by Damien Lespiau · 10 years ago
  31. 5d374d9 drm/i915/skl: Reduce the indentation level in skl_write_wm_values() by Damien Lespiau · 10 years ago
  32. afb024a drm/i915/skl: Correctly align skl_compute_plane_wm() arguments by Damien Lespiau · 10 years ago
  33. 9414f56 drm/i915/skl: Rework when the transition WMs are computed by Damien Lespiau · 10 years ago
  34. 407b50f drm/i915/skl: Move all the WM compute functions in one place by Damien Lespiau · 10 years ago
  35. e6d6617 drm/i915/skl: Make res_blocks/lines intermediate values 32 bits by Damien Lespiau · 10 years ago
  36. 21fca25 drm/i915/skl: Use a more descriptive parameter name in skl_compute_plane_wm() by Damien Lespiau · 10 years ago
  37. 16160e3 drm/i915/skl: Make 'end' of the DDB allocation entry exclusive by Damien Lespiau · 10 years ago
  38. 08db665 drm/i915/skl: Check the DDB state at modeset by Damien Lespiau · 10 years ago
  39. a269c58 drm/i915/skl: Read back the DDB allocation hw state by Damien Lespiau · 10 years ago
  40. 53b0deb drm/i915/skl: Store the new WM state at the very end of the update by Damien Lespiau · 10 years ago
  41. 4f94738 drm/i915/gen9: Disable WM if corresponding latency is 0 by Vandana Kannan · 10 years ago
  42. 367294b drm/i915/gen9: Add 2us read latency to WM level by Vandana Kannan · 10 years ago
  43. 3078999 drm/i915/skl: Read the pipe WM HW state by Pradeep Bhat · 10 years ago
  44. 8211bd5 drm/i915/skl: Program the DDB allocation by Damien Lespiau · 10 years ago
  45. b9cec07 drm/i915/skl: Allocate DDB portions for display planes by Damien Lespiau · 10 years ago
  46. 2d41c0b drm/i915/skl: SKL Watermark Computation by Pradeep Bhat · 10 years ago
  47. 2ac96d2 drm/i915/skl: Definition of SKL WM param structs for pipe/plane by Pradeep Bhat · 10 years ago
  48. 2af30a5 drm/i915/skl: Read the Memory Latency Values for WM computation by Pradeep Bhat · 10 years ago
  49. 5e56ba4 drm/i915/chv: Use 16 and 32 for low and high drain latency precision. by Rodrigo Vivi · 10 years ago
  50. 101b376 drm/i915/bdw: Remove BDW preproduction W/As until C stepping. by Rodrigo Vivi · 10 years ago
  51. 58abf1d drm/i915: Do not export RC6p and RC6pp if they don't exist by Rodrigo Vivi · 10 years ago
  52. a8cbd45 Merge branch 'drm-intel-next-fixes' into drm-intel-next by Daniel Vetter · 10 years ago
  53. 2aeb7d3 drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/ by Daniel Vetter · 10 years ago
  54. 9c065a7 drm/i915: Extract intel_runtime_pm.c by Daniel Vetter · 10 years ago
  55. 955e36d Merge branch 'topic/skl-stage1' into drm-intel-next-queued by Daniel Vetter · 10 years ago
  56. 6795686 drm/i915: Don't spam dmesg with rps messages on vlv/chv by Ville Syrjälä · 10 years ago
  57. 7526ed7 Revert "drm/i915/bdw: BDW Software Turbo" by Daniel Vetter · 10 years ago
  58. 1d73c2a drm/i915: Minimize the huge amount of unecessary fbc sw cache clean. by Rodrigo Vivi · 10 years ago
  59. c83155a drm/i915/skl: Move gen9 pm initialization into its own branch by Damien Lespiau · 11 years ago
  60. 3ca5da4 drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:skl by Damien Lespiau · 11 years ago
  61. 91e41d1 drm/i915/skl: Implement Wa4x4STCOptimizationDisable:skl by Damien Lespiau · 11 years ago
  62. acd5c34 drm/i915/skl: Implement WaDisableSDEUnitClockGating:skl by Damien Lespiau · 11 years ago
  63. 08524a9f drm/i915/skl: Restore pipe B/C interrupts by Satheeshakrishna M · 11 years ago
  64. da2078c drm/i915/skl: Provide a placeholder for init_clock_gating() by Damien Lespiau · 12 years ago
  65. 9adccc6 drm/i915: add SW tracking to FBC enabling by Paulo Zanoni · 10 years ago
  66. d2dee86 drm/i915: extract intel_init_fbc() by Paulo Zanoni · 10 years ago
  67. 342e36c drm/i915: Avoid reading fbc registers in vain when fbc was never enabled. by Rodrigo Vivi · 10 years ago
  68. 01d06e9 drm/i915: Only flush fbc on sw when fbc is enabled. by Rodrigo Vivi · 10 years ago
  69. d6feb19 drm/i915: Limit the watermark to at least 8 entries on gen2/3 by Ville Syrjälä · 10 years ago
  70. 773538e8 drm/i915: Reset power sequencer pipe tracking when disp2d is off by Ville Syrjälä · 10 years ago
  71. 5aef600 drm/i915: Rename global latency_ns variable by Chris Wilson · 10 years ago
  72. 1038392 drm/i915: Disable trickle feed for gen2/3 by Ville Syrjälä · 10 years ago
  73. 9d53910 drm/i915: Fix gen2 planes B and C max watermark value by Ville Syrjälä · 10 years ago
  74. 00e1e62 drm/i915: Init some CHV workarounds via LRIs in ring->init_context() by Ville Syrjälä · 10 years ago
  75. 1c14762 drm/i915: Warn about odd rps values on CHV by Ville Syrjälä · 10 years ago
  76. c76bb61 drm/i915/bdw: BDW Software Turbo by Daisy Sun · 10 years ago
  77. 2bb25c1 drm/i915: Populate mem_freq in init_gt_powerwave() by Ville Syrjälä · 10 years ago
  78. 86d7f23 drm/i915/bdw: Apply workarounds in render ring init function by Arun Siluvery · 10 years ago
  79. c5ad011 drm/i915: FBC flush nuke for BDW by Rodrigo Vivi · 10 years ago
  80. 47c2bd9 drm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gating by Paulo Zanoni · 10 years ago
  81. 89d6b2b drm/i915: call lpt_init_clock_gating on BDW too by Paulo Zanoni · 10 years ago
  82. 98a2e5f drm/i915: Bring UP Power Wells before disabling RC6. by Deepak S · 10 years ago
  83. 055e393 drm/i915: Use dev_priv as first argument of for_each_pipe() by Damien Lespiau · 10 years ago
  84. 48404c1 drm/i915: Add 180 degree primary plane rotation support by Sonika Jindal · 10 years ago
  85. a18b29f Merge tag 'drm-intel-next-2014-09-01' of git://anongit.freedesktop.org/drm-intel into drm-next by Dave Airlie · 10 years ago
  86. d5a0f2e Merge tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-intel into drm-next by Dave Airlie · 10 years ago
  87. 1bee201 drm/i915: Remove set but unused 'gt_perf_status' by Damien Lespiau · 10 years ago
  88. 889fa782 Merge tag 'drm-intel-fixes-2014-08-08' of git://anongit.freedesktop.org/drm-intel by Linus Torvalds · 10 years ago
  89. 01e184c drm/i915: Add sprite watermark programming for VLV and CHV by Gajanan Bhat · 10 years ago
  90. a398e9c drm/i915: Round-up clock and limit drain latency by Gajanan Bhat · 10 years ago
  91. 0948c26 drm/i915: Generalize drain latency computation by Gajanan Bhat · 10 years ago
  92. efd814b drm/i915: Polish the chv cmnlane resrt macros by Ville Syrjälä · 11 years ago
  93. 3dd7b974 drm/i915: Hack to tie both common lanes together on chv by Ville Syrjälä · 11 years ago
  94. 3c2777f drm/i915: Add cherryview_update_wm() by Ville Syrjälä · 11 years ago
  95. 41aad81 drm/i915: Update DDL only for current CRTC by Gajanan Bhat · 10 years ago
  96. 1abc4dc drm/i915: Parametrize VLV_DDL registers by Ville Syrjälä · 11 years ago
  97. 0a56067 drm/i915: Fill out the FWx watermark register defines by Ville Syrjälä · 11 years ago
  98. da46f93 drm/i915: Introduce FBC False Color for debug purposes. by Rodrigo Vivi · 10 years ago
  99. a504345 drm/i915: Split a few long debug prints by Ville Syrjälä · 11 years ago
  100. 2ce147f drm/i915: Add chv port D TX wells by Ville Syrjälä · 11 years ago