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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 24e3a7fb60a9187e5df90e5fa655ffc94b9c4f77 / arch / riscv
  1. 3b62de2 RISC-V: Fixes for clean allmodconfig build by Palmer Dabbelt · 7 years ago
  2. 7382fbd RISC-V: __io_writes should respect the length argument by Palmer Dabbelt · 7 years ago
  3. 07f8ba7 RISC-V: User-Visible Changes by Palmer Dabbelt · 7 years ago
  4. da894ff RISC-V: __io_writes should respect the length argument by Palmer Dabbelt · 7 years ago
  5. 0e710ac RISC-V: Clean up an unused include by Palmer Dabbelt · 7 years ago
  6. 921ebd8 RISC-V: Allow userspace to flush the instruction cache by Andrew Waterman · 7 years ago
  7. 08f051e RISC-V: Flush I$ when making a dirty page executable by Andrew Waterman · 7 years ago
  8. 741fc3f RISC-V: Add missing include by Olof Johansson · 7 years ago
  9. 4a41d5d RISC-V: Use define for get_cycles like other architectures by Olof Johansson · 7 years ago
  10. 4bde632 RISC-V: Provide stub of setup_profiling_timer() by Olof Johansson · 7 years ago
  11. 24948b7 RISC-V: Export some expected symbols for modules by Olof Johansson · 7 years ago
  12. 83e7b87 RISC-V: move empty_zero_page definition to C and export it by Olof Johansson · 7 years ago
  13. fe2726a RISC-V: io.h: type fixes for warnings by Olof Johansson · 7 years ago
  14. 5e6f82b RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros by Olof Johansson · 7 years ago
  15. 5ddf755 RISC-V: use generic serial.h by Olof Johansson · 7 years ago
  16. bf73055 RISC-V: remove spin_unlock_wait() by Palmer Dabbelt · 7 years ago
  17. c901e45 RISC-V: `sfence.vma` orderes the instruction cache by Palmer Dabbelt · 7 years ago
  18. 21db403 RISC-V: Add READ_ONCE in arch_spin_is_locked() by Palmer Dabbelt · 7 years ago
  19. 9347ce5 RISC-V: __test_and_op_bit_ord should be strongly ordered by Palmer Dabbelt · 7 years ago
  20. 3343eb6 RISC-V: Remove smb_mb__{before,after}_spinlock() by Palmer Dabbelt · 7 years ago
  21. 61a60d3 RISC-V: Remove __smp_bp__{before,after}_atomic by Palmer Dabbelt · 7 years ago
  22. 8286d51 RISC-V: Comment on why {,cmp}xchg is ordered how it is by Palmer Dabbelt · 7 years ago
  23. 4650d02 RISC-V: Remove unused arguments from ATOMIC_OP by Palmer Dabbelt · 7 years ago
  24. 28dfbe6 RISC-V: Add VDSO entries for clock_get/gettimeofday/getcpu by Andrew Waterman · 7 years ago
  25. b7e5a59 RISC-V: Remove __vdso_cmpxchg{32,64} symbol versions by Palmer Dabbelt · 7 years ago
  26. b293fca Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux by Linus Torvalds · 7 years ago
  27. fbe934d RISC-V: Build Infrastructure by Palmer Dabbelt · 8 years ago
  28. e2c0cdf RISC-V: User-facing API by Palmer Dabbelt · 8 years ago
  29. 07037db RISC-V: Paging and MMU by Palmer Dabbelt · 8 years ago
  30. 6d60b6e RISC-V: Device, timer, IRQs, and the SBI by Palmer Dabbelt · 8 years ago
  31. 7db91e5 RISC-V: Task implementation by Palmer Dabbelt · 8 years ago
  32. 2129a23 RISC-V: ELF and module implementation by Palmer Dabbelt · 8 years ago
  33. 5d8544e RISC-V: Generic library routines and assembly by Palmer Dabbelt · 8 years ago
  34. fab957c RISC-V: Atomic and Locking Code by Palmer Dabbelt · 8 years ago
  35. 76d2a04 RISC-V: Init and Halt Code by Palmer Dabbelt · 8 years ago