1. 0146337 Merge tag 'cpu-to-thread_info-v5.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux by Linus Torvalds · 3 years, 3 months ago
  2. 7ecbc64 irq: riscv: perform irqentry in entry code by Mark Rutland · 3 years, 3 months ago
  3. 8aa0fb0 riscv: rely on core code to keep thread_info::cpu updated by Ard Biesheuvel · 3 years, 4 months ago
  4. 31da94c riscv: add VMAP_STACK overflow detection by Tong Tiangen · 3 years, 7 months ago
  5. 939b7cb Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux by Linus Torvalds · 3 years, 8 months ago
  6. 800149a riscv: sifive: Apply errata "cip-453" patch by Vincent Chen · 3 years, 10 months ago
  7. 7ae1163 riscv: keep interrupts disabled for BREAKPOINT exception by Jisheng Zhang · 3 years, 10 months ago
  8. ac8d0b9 riscv,entry: fix misaligned base for excp_vect_table by Zihao Yu · 3 years, 10 months ago
  9. 7cd1af1 riscv: Trace irq on only interrupt is enabled by Atish Patra · 4 years, 1 month ago
  10. 643437b riscv: Enable interrupts during syscalls with M-Mode by Damien Le Moal · 4 years, 1 month ago
  11. cf7b2ae riscv: return -ENOSYS for syscall -1 by Andreas Schwab · 4 years, 1 month ago
  12. 3e7b669 riscv: Cleanup unnecessary define in asm-offset.c by Guo Ren · 4 years, 6 months ago
  13. ed48b29 riscv: Enable context tracking by Greentime Hu · 4 years, 7 months ago
  14. 3c46979 riscv: Enable LOCKDEP_SUPPORT & fixup TRACE_IRQFLAGS_SUPPORT by Guo Ren · 4 years, 7 months ago
  15. 24dc170 RISC-V: Remove do_IRQ() function by Anup Patel · 4 years, 8 months ago
  16. eab4002 Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux by Linus Torvalds · 4 years, 9 months ago
  17. af33d24 riscv: fix seccomp reject syscall code path by Tycho Andersen · 5 years ago
  18. fdff991 RISC-V: Inline the assembly register save/restore macros by Palmer Dabbelt · 4 years, 11 months ago
  19. c677124 Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip by Linus Torvalds · 5 years ago
  20. 556f47a riscv: reject invalid syscalls below -1 by David Abdurachmanov · 5 years ago
  21. 29ff649 sched/rt, riscv: Use CONFIG_PREEMPTION by Thomas Gleixner · 5 years ago
  22. 5ba9aa5 Merge branch 'next/nommu' into for-next by Paul Walmsley · 5 years ago
  23. 6bd33e1 riscv: add nommu support by Christoph Hellwig · 5 years ago
  24. a4c3733 riscv: abstract out CSR names for supervisor vs machine mode by Christoph Hellwig · 5 years ago
  25. 5340627 riscv: add support for SECCOMP and SECCOMP_FILTER by David Abdurachmanov · 5 years ago
  26. cd9e72b8 RISC-V: entry: Remove unneeded need_resched() loop by Valentin Schneider · 5 years ago
  27. 1885660 RISC-V: Clear load reservations while restoring hart contexts by Palmer Dabbelt · 5 years ago
  28. c82dd6d riscv: Avoid interrupts being erroneously enabled in handle_exception() by Vincent Chen · 5 years ago
  29. 4f3f900 riscv: Using CSR numbers to access CSRs by Bin Meng · 5 years ago
  30. 50acfb2 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 by Thomas Gleixner · 6 years ago
  31. a3182c9 RISC-V: Access CSRs using CSR numbers by Anup Patel · 6 years ago
  32. 99fd6e8 RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=y by Vincent Chen · 6 years ago
  33. efe75c4 riscv: add audit support by David Abdurachmanov · 6 years ago
  34. d26c4bb RISC-V: SMP cleanup and new features by Palmer Dabbelt · 6 years ago
  35. 1ed4237 RISC-V: No need to pass scause as arg to do_IRQ() by Anup Patel · 6 years ago
  36. e68ad86 Extract FPU context operations from entry.S by Alan Kao · 6 years ago
  37. 6ea0f26 RISC-V: implement low-level interrupt handling by Christoph Hellwig · 6 years ago
  38. cc6c984 RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler by Palmer Dabbelt · 7 years ago
  39. bcae803 RISC-V: Enable IRQ during exception handling by zongbox@gmail.com · 7 years ago
  40. fe9b842 riscv: disable SUM in the exception handler by Christoph Hellwig · 7 years ago
  41. 1125203 riscv: rename SR_* constants to match the spec by Christoph Hellwig · 7 years ago
  42. 7db91e5 RISC-V: Task implementation by Palmer Dabbelt · 8 years ago