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Catalin Marinasb3901d52012-03-05 11:49:28 +00001/*
2 * Based on arch/arm/kernel/process.c
3 *
4 * Original Copyright (C) 1995 Linus Torvalds
5 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <stdarg.h>
22
23#include <linux/export.h>
24#include <linux/sched.h>
25#include <linux/kernel.h>
26#include <linux/mm.h>
27#include <linux/stddef.h>
28#include <linux/unistd.h>
29#include <linux/user.h>
30#include <linux/delay.h>
31#include <linux/reboot.h>
32#include <linux/interrupt.h>
33#include <linux/kallsyms.h>
34#include <linux/init.h>
35#include <linux/cpu.h>
36#include <linux/elfcore.h>
37#include <linux/pm.h>
38#include <linux/tick.h>
39#include <linux/utsname.h>
40#include <linux/uaccess.h>
41#include <linux/random.h>
42#include <linux/hw_breakpoint.h>
43#include <linux/personality.h>
44#include <linux/notifier.h>
45
46#include <asm/compat.h>
47#include <asm/cacheflush.h>
Will Deaconec45d1c2013-01-17 12:31:45 +000048#include <asm/fpsimd.h>
49#include <asm/mmu_context.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000050#include <asm/processor.h>
51#include <asm/stacktrace.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000052
53static void setup_restart(void)
54{
55 /*
56 * Tell the mm system that we are going to reboot -
57 * we may need it to insert some 1:1 mappings so that
58 * soft boot works.
59 */
60 setup_mm_for_reboot();
61
62 /* Clean and invalidate caches */
63 flush_cache_all();
64
65 /* Turn D-cache off */
66 cpu_cache_off();
67
68 /* Push out any further dirty data, and ensure cache is empty */
69 flush_cache_all();
70}
71
72void soft_restart(unsigned long addr)
73{
Geoff Levand09024aa2013-12-17 00:19:29 +000074 typedef void (*phys_reset_t)(unsigned long);
75 phys_reset_t phys_reset;
76
Catalin Marinasb3901d52012-03-05 11:49:28 +000077 setup_restart();
Geoff Levand09024aa2013-12-17 00:19:29 +000078
79 /* Switch to the identity mapping */
80 phys_reset = (phys_reset_t)virt_to_phys(cpu_reset);
81 phys_reset(addr);
82
83 /* Should never get here */
84 BUG();
Catalin Marinasb3901d52012-03-05 11:49:28 +000085}
86
87/*
88 * Function pointers to optional machine specific functions
89 */
90void (*pm_power_off)(void);
91EXPORT_SYMBOL_GPL(pm_power_off);
92
Catalin Marinasb0946fc2013-07-23 11:05:10 +010093void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000094EXPORT_SYMBOL_GPL(arm_pm_restart);
Catalin Marinasb3901d52012-03-05 11:49:28 +000095
Catalin Marinasb3901d52012-03-05 11:49:28 +000096/*
97 * This is our default idle handler.
98 */
Thomas Gleixner00872982013-03-21 22:49:39 +010099void arch_cpu_idle(void)
Catalin Marinasb3901d52012-03-05 11:49:28 +0000100{
101 /*
102 * This should do all the clock switching and wait for interrupt
103 * tricks
104 */
Nicolas Pitre69905662014-02-17 10:59:30 -0500105 cpu_do_idle();
106 local_irq_enable();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000107}
108
Mark Rutland9327e2c2013-10-24 20:30:18 +0100109#ifdef CONFIG_HOTPLUG_CPU
110void arch_cpu_idle_dead(void)
111{
112 cpu_die();
113}
114#endif
115
Catalin Marinasb3901d52012-03-05 11:49:28 +0000116void machine_shutdown(void)
117{
118#ifdef CONFIG_SMP
119 smp_send_stop();
120#endif
121}
122
123void machine_halt(void)
124{
125 machine_shutdown();
126 while (1);
127}
128
129void machine_power_off(void)
130{
131 machine_shutdown();
132 if (pm_power_off)
133 pm_power_off();
134}
135
136void machine_restart(char *cmd)
137{
138 machine_shutdown();
139
140 /* Disable interrupts first */
141 local_irq_disable();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000142
143 /* Now call the architecture specific reboot code. */
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000144 if (arm_pm_restart)
Marc Zyngierff701302013-07-11 12:13:00 +0100145 arm_pm_restart(reboot_mode, cmd);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000146
147 /*
148 * Whoops - the architecture was unable to reboot.
149 */
150 printk("Reboot failed -- System halted\n");
151 while (1);
152}
153
154void __show_regs(struct pt_regs *regs)
155{
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100156 int i, top_reg;
157 u64 lr, sp;
158
159 if (compat_user_mode(regs)) {
160 lr = regs->compat_lr;
161 sp = regs->compat_sp;
162 top_reg = 12;
163 } else {
164 lr = regs->regs[30];
165 sp = regs->sp;
166 top_reg = 29;
167 }
Catalin Marinasb3901d52012-03-05 11:49:28 +0000168
Tejun Heoa43cb952013-04-30 15:27:17 -0700169 show_regs_print_info(KERN_DEFAULT);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000170 print_symbol("PC is at %s\n", instruction_pointer(regs));
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100171 print_symbol("LR is at %s\n", lr);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000172 printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100173 regs->pc, lr, regs->pstate);
174 printk("sp : %016llx\n", sp);
175 for (i = top_reg; i >= 0; i--) {
Catalin Marinasb3901d52012-03-05 11:49:28 +0000176 printk("x%-2d: %016llx ", i, regs->regs[i]);
177 if (i % 2 == 0)
178 printk("\n");
179 }
180 printk("\n");
181}
182
183void show_regs(struct pt_regs * regs)
184{
185 printk("\n");
Catalin Marinasb3901d52012-03-05 11:49:28 +0000186 __show_regs(regs);
187}
188
189/*
190 * Free current thread data structures etc..
191 */
192void exit_thread(void)
193{
194}
195
196void flush_thread(void)
197{
198 fpsimd_flush_thread();
199 flush_ptrace_hw_breakpoint(current);
200}
201
202void release_thread(struct task_struct *dead_task)
203{
204}
205
206int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
207{
208 fpsimd_save_state(&current->thread.fpsimd_state);
209 *dst = *src;
210 return 0;
211}
212
213asmlinkage void ret_from_fork(void) asm("ret_from_fork");
214
215int copy_thread(unsigned long clone_flags, unsigned long stack_start,
Al Viroafa86fc2012-10-22 22:51:14 -0400216 unsigned long stk_sz, struct task_struct *p)
Catalin Marinasb3901d52012-03-05 11:49:28 +0000217{
218 struct pt_regs *childregs = task_pt_regs(p);
219 unsigned long tls = p->thread.tp_value;
220
Catalin Marinasb3901d52012-03-05 11:49:28 +0000221 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
Catalin Marinasb3901d52012-03-05 11:49:28 +0000222
Al Viro9ac08002012-10-21 15:56:52 -0400223 if (likely(!(p->flags & PF_KTHREAD))) {
224 *childregs = *current_pt_regs();
Catalin Marinasc34501d2012-10-05 12:31:20 +0100225 childregs->regs[0] = 0;
226 if (is_compat_thread(task_thread_info(p))) {
Al Viroe0fd18c2012-10-18 00:55:54 -0400227 if (stack_start)
228 childregs->compat_sp = stack_start;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100229 } else {
230 /*
231 * Read the current TLS pointer from tpidr_el0 as it may be
232 * out-of-sync with the saved value.
233 */
234 asm("mrs %0, tpidr_el0" : "=r" (tls));
Al Viroe0fd18c2012-10-18 00:55:54 -0400235 if (stack_start) {
236 /* 16-byte aligned stack mandatory on AArch64 */
237 if (stack_start & 15)
238 return -EINVAL;
239 childregs->sp = stack_start;
240 }
Catalin Marinasc34501d2012-10-05 12:31:20 +0100241 }
242 /*
243 * If a TLS pointer was passed to clone (4th argument), use it
244 * for the new thread.
245 */
246 if (clone_flags & CLONE_SETTLS)
Al Viro9ac08002012-10-21 15:56:52 -0400247 tls = childregs->regs[3];
Catalin Marinasc34501d2012-10-05 12:31:20 +0100248 } else {
249 memset(childregs, 0, sizeof(struct pt_regs));
250 childregs->pstate = PSR_MODE_EL1h;
251 p->thread.cpu_context.x19 = stack_start;
252 p->thread.cpu_context.x20 = stk_sz;
253 }
254 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
255 p->thread.cpu_context.sp = (unsigned long)childregs;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000256 p->thread.tp_value = tls;
257
258 ptrace_hw_copy_thread(p);
259
260 return 0;
261}
262
263static void tls_thread_switch(struct task_struct *next)
264{
265 unsigned long tpidr, tpidrro;
266
267 if (!is_compat_task()) {
268 asm("mrs %0, tpidr_el0" : "=r" (tpidr));
269 current->thread.tp_value = tpidr;
270 }
271
272 if (is_compat_thread(task_thread_info(next))) {
273 tpidr = 0;
274 tpidrro = next->thread.tp_value;
275 } else {
276 tpidr = next->thread.tp_value;
277 tpidrro = 0;
278 }
279
280 asm(
281 " msr tpidr_el0, %0\n"
282 " msr tpidrro_el0, %1"
283 : : "r" (tpidr), "r" (tpidrro));
284}
285
286/*
287 * Thread switching.
288 */
289struct task_struct *__switch_to(struct task_struct *prev,
290 struct task_struct *next)
291{
292 struct task_struct *last;
293
294 fpsimd_thread_switch(next);
295 tls_thread_switch(next);
296 hw_breakpoint_thread_switch(next);
Christopher Covington33257322013-04-03 19:01:01 +0100297 contextidr_thread_switch(next);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000298
Catalin Marinas5108c672013-04-24 14:47:02 +0100299 /*
300 * Complete any pending TLB or cache maintenance on this CPU in case
301 * the thread migrates to a different CPU.
302 */
Will Deacon98f76852014-05-02 16:24:10 +0100303 dsb(ish);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000304
305 /* the actual thread switch */
306 last = cpu_switch_to(prev, next);
307
308 return last;
309}
310
Catalin Marinasb3901d52012-03-05 11:49:28 +0000311unsigned long get_wchan(struct task_struct *p)
312{
313 struct stackframe frame;
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000314 unsigned long stack_page;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000315 int count = 0;
316 if (!p || p == current || p->state == TASK_RUNNING)
317 return 0;
318
319 frame.fp = thread_saved_fp(p);
320 frame.sp = thread_saved_sp(p);
321 frame.pc = thread_saved_pc(p);
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000322 stack_page = (unsigned long)task_stack_page(p);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000323 do {
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000324 if (frame.sp < stack_page ||
325 frame.sp >= stack_page + THREAD_SIZE ||
326 unwind_frame(&frame))
Catalin Marinasb3901d52012-03-05 11:49:28 +0000327 return 0;
328 if (!in_sched_functions(frame.pc))
329 return frame.pc;
330 } while (count ++ < 16);
331 return 0;
332}
333
334unsigned long arch_align_stack(unsigned long sp)
335{
336 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
337 sp -= get_random_int() & ~PAGE_MASK;
338 return sp & ~0xf;
339}
340
341static unsigned long randomize_base(unsigned long base)
342{
343 unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1;
344 return randomize_range(base, range_end, 0) ? : base;
345}
346
347unsigned long arch_randomize_brk(struct mm_struct *mm)
348{
349 return randomize_base(mm->brk);
350}
351
352unsigned long randomize_et_dyn(unsigned long base)
353{
354 return randomize_base(base);
355}