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Akhil Bhansalie67f86b2013-10-15 14:19:07 -06001/* Copyright 2012 STEC, Inc.
2 *
3 * This file is licensed under the terms of the 3-clause
4 * BSD License (http://opensource.org/licenses/BSD-3-Clause)
5 * or the GNU GPL-2.0 (http://www.gnu.org/licenses/gpl-2.0.html),
6 * at your option. Both licenses are also available in the LICENSE file
7 * distributed with this project. This file may not be copied, modified,
8 * or distributed except in accordance with those terms.
9 */
10
11
12#ifndef SKD_S1120_H
13#define SKD_S1120_H
14
15#pragma pack(push, s1120_h, 1)
16
17/*
18 * Q-channel, 64-bit r/w
19 */
20#define FIT_Q_COMMAND 0x400u
21#define FIT_QCMD_QID_MASK (0x3 << 1)
22#define FIT_QCMD_QID0 (0x0 << 1)
23#define FIT_QCMD_QID_NORMAL FIT_QCMD_QID0
Akhil Bhansalie67f86b2013-10-15 14:19:07 -060024#define FIT_QCMD_QID1 (0x1 << 1)
25#define FIT_QCMD_QID2 (0x2 << 1)
26#define FIT_QCMD_QID3 (0x3 << 1)
Akhil Bhansalie67f86b2013-10-15 14:19:07 -060027#define FIT_QCMD_FLUSH_QUEUE (0ull) /* add QID */
28#define FIT_QCMD_MSGSIZE_MASK (0x3 << 4)
29#define FIT_QCMD_MSGSIZE_64 (0x0 << 4)
30#define FIT_QCMD_MSGSIZE_128 (0x1 << 4)
31#define FIT_QCMD_MSGSIZE_256 (0x2 << 4)
32#define FIT_QCMD_MSGSIZE_512 (0x3 << 4)
33#define FIT_QCMD_BASE_ADDRESS_MASK (0xFFFFFFFFFFFFFFC0ull)
34
35
36/*
37 * Control, 32-bit r/w
38 */
39#define FIT_CONTROL 0x500u
Akhil Bhansalie67f86b2013-10-15 14:19:07 -060040#define FIT_CR_HARD_RESET (1u << 0u)
Akhil Bhansalie67f86b2013-10-15 14:19:07 -060041#define FIT_CR_SOFT_RESET (1u << 1u)
Akhil Bhansalie67f86b2013-10-15 14:19:07 -060042#define FIT_CR_DIS_TIMESTAMPS (1u << 6u)
Akhil Bhansalie67f86b2013-10-15 14:19:07 -060043#define FIT_CR_ENABLE_INTERRUPTS (1u << 7u)
44
45/*
46 * Status, 32-bit, r/o
47 */
48#define FIT_STATUS 0x510u
49#define FIT_SR_DRIVE_STATE_MASK 0x000000FFu
Akhil Bhansalie67f86b2013-10-15 14:19:07 -060050#define FIT_SR_SIGNATURE (0xFF << 8)
51#define FIT_SR_PIO_DMA (1 << 16)
Akhil Bhansalie67f86b2013-10-15 14:19:07 -060052#define FIT_SR_DRIVE_OFFLINE 0x00
53#define FIT_SR_DRIVE_INIT 0x01
54/* #define FIT_SR_DRIVE_READY 0x02 */
55#define FIT_SR_DRIVE_ONLINE 0x03
56#define FIT_SR_DRIVE_BUSY 0x04
57#define FIT_SR_DRIVE_FAULT 0x05
58#define FIT_SR_DRIVE_DEGRADED 0x06
59#define FIT_SR_PCIE_LINK_DOWN 0x07
60#define FIT_SR_DRIVE_SOFT_RESET 0x08
61#define FIT_SR_DRIVE_INIT_FAULT 0x09
62#define FIT_SR_DRIVE_BUSY_SANITIZE 0x0A
63#define FIT_SR_DRIVE_BUSY_ERASE 0x0B
64#define FIT_SR_DRIVE_FW_BOOTING 0x0C
65#define FIT_SR_DRIVE_NEED_FW_DOWNLOAD 0xFE
66#define FIT_SR_DEVICE_MISSING 0xFF
67#define FIT_SR__RESERVED 0xFFFFFF00u
68
Akhil Bhansalie67f86b2013-10-15 14:19:07 -060069/*
70 * FIT_STATUS - Status register data definition
71 */
72#define FIT_SR_STATE_MASK (0xFF << 0)
73#define FIT_SR_SIGNATURE (0xFF << 8)
74#define FIT_SR_PIO_DMA (1 << 16)
Akhil Bhansalie67f86b2013-10-15 14:19:07 -060075
76
77/*
78 * Interrupt status, 32-bit r/w1c (w1c ==> write 1 to clear)
79 */
80#define FIT_INT_STATUS_HOST 0x520u
81#define FIT_ISH_FW_STATE_CHANGE (1u << 0u)
82#define FIT_ISH_COMPLETION_POSTED (1u << 1u)
83#define FIT_ISH_MSG_FROM_DEV (1u << 2u)
84#define FIT_ISH_UNDEFINED_3 (1u << 3u)
85#define FIT_ISH_UNDEFINED_4 (1u << 4u)
86#define FIT_ISH_Q0_FULL (1u << 5u)
87#define FIT_ISH_Q1_FULL (1u << 6u)
88#define FIT_ISH_Q2_FULL (1u << 7u)
89#define FIT_ISH_Q3_FULL (1u << 8u)
90#define FIT_ISH_QCMD_FIFO_OVERRUN (1u << 9u)
91#define FIT_ISH_BAD_EXP_ROM_READ (1u << 10u)
92
93
94#define FIT_INT_DEF_MASK \
95 (FIT_ISH_FW_STATE_CHANGE | \
96 FIT_ISH_COMPLETION_POSTED | \
97 FIT_ISH_MSG_FROM_DEV | \
98 FIT_ISH_Q0_FULL | \
99 FIT_ISH_Q1_FULL | \
100 FIT_ISH_Q2_FULL | \
101 FIT_ISH_Q3_FULL | \
102 FIT_ISH_QCMD_FIFO_OVERRUN | \
103 FIT_ISH_BAD_EXP_ROM_READ)
104
105#define FIT_INT_QUEUE_FULL \
106 (FIT_ISH_Q0_FULL | \
107 FIT_ISH_Q1_FULL | \
108 FIT_ISH_Q2_FULL | \
109 FIT_ISH_Q3_FULL)
110
111
112#define MSI_MSG_NWL_ERROR_0 0x00000000
113#define MSI_MSG_NWL_ERROR_1 0x00000001
114#define MSI_MSG_NWL_ERROR_2 0x00000002
115#define MSI_MSG_NWL_ERROR_3 0x00000003
116#define MSI_MSG_STATE_CHANGE 0x00000004
117#define MSI_MSG_COMPLETION_POSTED 0x00000005
118#define MSI_MSG_MSG_FROM_DEV 0x00000006
119#define MSI_MSG_RESERVED_0 0x00000007
120#define MSI_MSG_RESERVED_1 0x00000008
121#define MSI_MSG_QUEUE_0_FULL 0x00000009
122#define MSI_MSG_QUEUE_1_FULL 0x0000000A
123#define MSI_MSG_QUEUE_2_FULL 0x0000000B
124#define MSI_MSG_QUEUE_3_FULL 0x0000000C
125
126
127
128#define FIT_INT_RESERVED_MASK \
129 (FIT_ISH_UNDEFINED_3 | \
130 FIT_ISH_UNDEFINED_4)
131/*
132 * Interrupt mask, 32-bit r/w
133 * Bit definitions are the same as FIT_INT_STATUS_HOST
134 */
135#define FIT_INT_MASK_HOST 0x528u
136
137
138/*
139 * Message to device, 32-bit r/w
140 */
141#define FIT_MSG_TO_DEVICE 0x540u
142
143/*
144 * Message from device, 32-bit, r/o
145 */
146#define FIT_MSG_FROM_DEVICE 0x548u
147
148
149/*
150 * 32-bit messages to/from device, composition/extraction macros
151 */
152#define FIT_MXD_CONS(TYPE, PARAM, DATA) \
153 ((((TYPE) & 0xFFu) << 24u) | \
154 (((PARAM) & 0xFFu) << 16u) | \
155 (((DATA) & 0xFFFFu) << 0u))
156#define FIT_MXD_TYPE(MXD) (((MXD) >> 24u) & 0xFFu)
157#define FIT_MXD_PARAM(MXD) (((MXD) >> 16u) & 0xFFu)
158#define FIT_MXD_DATA(MXD) (((MXD) >> 0u) & 0xFFFFu)
159
160
161/*
162 * Types of messages to/from device
163 */
164#define FIT_MTD_FITFW_INIT 0x01u
165#define FIT_MTD_GET_CMDQ_DEPTH 0x02u
166#define FIT_MTD_SET_COMPQ_DEPTH 0x03u
167#define FIT_MTD_SET_COMPQ_ADDR 0x04u
168#define FIT_MTD_ARM_QUEUE 0x05u
169#define FIT_MTD_CMD_LOG_HOST_ID 0x07u
170#define FIT_MTD_CMD_LOG_TIME_STAMP_LO 0x08u
171#define FIT_MTD_CMD_LOG_TIME_STAMP_HI 0x09u
172#define FIT_MFD_SMART_EXCEEDED 0x10u
173#define FIT_MFD_POWER_DOWN 0x11u
174#define FIT_MFD_OFFLINE 0x12u
175#define FIT_MFD_ONLINE 0x13u
176#define FIT_MFD_FW_RESTARTING 0x14u
177#define FIT_MFD_PM_ACTIVE 0x15u
178#define FIT_MFD_PM_STANDBY 0x16u
179#define FIT_MFD_PM_SLEEP 0x17u
180#define FIT_MFD_CMD_PROGRESS 0x18u
181
Akhil Bhansalie67f86b2013-10-15 14:19:07 -0600182#define FIT_MTD_DEBUG 0xFEu
183#define FIT_MFD_DEBUG 0xFFu
Akhil Bhansalie67f86b2013-10-15 14:19:07 -0600184
185#define FIT_MFD_MASK (0xFFu)
186#define FIT_MFD_DATA_MASK (0xFFu)
187#define FIT_MFD_MSG(x) (((x) >> 24) & FIT_MFD_MASK)
188#define FIT_MFD_DATA(x) ((x) & FIT_MFD_MASK)
189
190
191/*
192 * Extra arg to FIT_MSG_TO_DEVICE, 64-bit r/w
193 * Used to set completion queue address (FIT_MTD_SET_COMPQ_ADDR)
194 * (was Response buffer in docs)
195 */
196#define FIT_MSG_TO_DEVICE_ARG 0x580u
197
198/*
199 * Hardware (ASIC) version, 32-bit r/o
200 */
201#define FIT_HW_VERSION 0x588u
202
203/*
204 * Scatter/gather list descriptor.
205 * 32-bytes and must be aligned on a 32-byte boundary.
206 * All fields are in little endian order.
207 */
208struct fit_sg_descriptor {
209 uint32_t control;
210 uint32_t byte_count;
211 uint64_t host_side_addr;
212 uint64_t dev_side_addr;
213 uint64_t next_desc_ptr;
214};
215
216#define FIT_SGD_CONTROL_NOT_LAST 0x000u
217#define FIT_SGD_CONTROL_LAST 0x40Eu
218
219/*
220 * Header at the beginning of a FIT message. The header
221 * is followed by SSDI requests each 64 bytes.
222 * A FIT message can be up to 512 bytes long and must start
223 * on a 64-byte boundary.
224 */
225struct fit_msg_hdr {
226 uint8_t protocol_id;
227 uint8_t num_protocol_cmds_coalesced;
228 uint8_t _reserved[62];
229};
230
231#define FIT_PROTOCOL_ID_FIT 1
232#define FIT_PROTOCOL_ID_SSDI 2
233#define FIT_PROTOCOL_ID_SOFIT 3
234
235
236#define FIT_PROTOCOL_MINOR_VER(mtd_val) ((mtd_val >> 16) & 0xF)
237#define FIT_PROTOCOL_MAJOR_VER(mtd_val) ((mtd_val >> 20) & 0xF)
238
Akhil Bhansalie67f86b2013-10-15 14:19:07 -0600239/*
240 * Format of a completion entry. The completion queue is circular
241 * and must have at least as many entries as the maximum number
242 * of commands that may be issued to the device.
243 *
244 * There are no head/tail pointers. The cycle value is used to
245 * infer the presence of new completion records.
246 * Initially the cycle in all entries is 0, the index is 0, and
247 * the cycle value to expect is 1. When completions are added
248 * their cycle values are set to 1. When the index wraps the
249 * cycle value to expect is incremented.
250 *
251 * Command_context is opaque and taken verbatim from the SSDI command.
252 * All other fields are big endian.
253 */
Akhil Bhansalie67f86b2013-10-15 14:19:07 -0600254#define FIT_PROTOCOL_VERSION_0 0
255
256/*
257 * Protocol major version 1 completion entry.
258 * The major protocol version is found in bits
259 * 20-23 of the FIT_MTD_FITFW_INIT response.
260 */
261struct fit_completion_entry_v1 {
262 uint32_t num_returned_bytes;
263 uint16_t tag;
264 uint8_t status; /* SCSI status */
265 uint8_t cycle;
266};
267#define FIT_PROTOCOL_VERSION_1 1
268#define FIT_PROTOCOL_VERSION_CURRENT FIT_PROTOCOL_VERSION_1
269
270struct fit_comp_error_info {
271 uint8_t type:7; /* 00: Bits0-6 indicates the type of sense data. */
272 uint8_t valid:1; /* 00: Bit 7 := 1 ==> info field is valid. */
273 uint8_t reserved0; /* 01: Obsolete field */
274 uint8_t key:4; /* 02: Bits0-3 indicate the sense key. */
275 uint8_t reserved2:1; /* 02: Reserved bit. */
276 uint8_t bad_length:1; /* 02: Incorrect Length Indicator */
277 uint8_t end_medium:1; /* 02: End of Medium */
278 uint8_t file_mark:1; /* 02: Filemark */
279 uint8_t info[4]; /* 03: */
280 uint8_t reserved1; /* 07: Additional Sense Length */
281 uint8_t cmd_spec[4]; /* 08: Command Specific Information */
282 uint8_t code; /* 0C: Additional Sense Code */
283 uint8_t qual; /* 0D: Additional Sense Code Qualifier */
284 uint8_t fruc; /* 0E: Field Replaceable Unit Code */
285 uint8_t sks_high:7; /* 0F: Sense Key Specific (MSB) */
286 uint8_t sks_valid:1; /* 0F: Sense Key Specific Valid */
287 uint16_t sks_low; /* 10: Sense Key Specific (LSW) */
288 uint16_t reserved3; /* 12: Part of additional sense bytes (unused) */
289 uint16_t uec; /* 14: Additional Sense Bytes */
290 uint64_t per; /* 16: Additional Sense Bytes */
291 uint8_t reserved4[2]; /* 1E: Additional Sense Bytes (unused) */
292};
293
294
295/* Task management constants */
296#define SOFT_TASK_SIMPLE 0x00
297#define SOFT_TASK_HEAD_OF_QUEUE 0x01
298#define SOFT_TASK_ORDERED 0x02
299
300
301/* Version zero has the last 32 bits reserved,
302 * Version one has the last 32 bits sg_list_len_bytes;
303 */
304struct skd_command_header {
305 uint64_t sg_list_dma_address;
306 uint16_t tag;
307 uint8_t attribute;
308 uint8_t add_cdb_len; /* In 32 bit words */
309 uint32_t sg_list_len_bytes;
310};
311
312struct skd_scsi_request {
313 struct skd_command_header hdr;
314 unsigned char cdb[16];
315/* unsigned char _reserved[16]; */
316};
317
318struct driver_inquiry_data {
319 uint8_t peripheral_device_type:5;
320 uint8_t qualifier:3;
321 uint8_t page_code;
322 uint16_t page_length;
323 uint16_t pcie_bus_number;
324 uint8_t pcie_device_number;
325 uint8_t pcie_function_number;
326 uint8_t pcie_link_speed;
327 uint8_t pcie_link_lanes;
328 uint16_t pcie_vendor_id;
329 uint16_t pcie_device_id;
330 uint16_t pcie_subsystem_vendor_id;
331 uint16_t pcie_subsystem_device_id;
332 uint8_t reserved1[2];
333 uint8_t reserved2[3];
334 uint8_t driver_version_length;
335 uint8_t driver_version[0x14];
336};
337
338#pragma pack(pop, s1120_h)
339
340#endif /* SKD_S1120_H */