Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Intel Multiprocessor Specification 1.1 and 1.4 |
| 3 | * compliant MP-table parsing routines. |
| 4 | * |
| 5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> |
| 6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> |
| 7 | * |
| 8 | * Fixes |
| 9 | * Erich Boleyn : MP v1.4 and additional changes. |
| 10 | * Alan Cox : Added EBDA scanning |
| 11 | * Ingo Molnar : various cleanups and rewrites |
| 12 | * Maciej W. Rozycki: Bits for default MP configurations |
| 13 | * Paul Diefenbaugh: Added full ACPI support |
| 14 | */ |
| 15 | |
| 16 | #include <linux/mm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #include <linux/init.h> |
| 18 | #include <linux/acpi.h> |
| 19 | #include <linux/delay.h> |
| 20 | #include <linux/config.h> |
| 21 | #include <linux/bootmem.h> |
| 22 | #include <linux/smp_lock.h> |
| 23 | #include <linux/kernel_stat.h> |
| 24 | #include <linux/mc146818rtc.h> |
| 25 | #include <linux/bitops.h> |
| 26 | |
| 27 | #include <asm/smp.h> |
| 28 | #include <asm/acpi.h> |
| 29 | #include <asm/mtrr.h> |
| 30 | #include <asm/mpspec.h> |
| 31 | #include <asm/io_apic.h> |
| 32 | |
| 33 | #include <mach_apic.h> |
| 34 | #include <mach_mpparse.h> |
| 35 | #include <bios_ebda.h> |
| 36 | |
| 37 | /* Have we found an MP table */ |
| 38 | int smp_found_config; |
| 39 | unsigned int __initdata maxcpus = NR_CPUS; |
| 40 | |
| 41 | /* |
| 42 | * Various Linux-internal data structures created from the |
| 43 | * MP-table. |
| 44 | */ |
| 45 | int apic_version [MAX_APICS]; |
| 46 | int mp_bus_id_to_type [MAX_MP_BUSSES]; |
| 47 | int mp_bus_id_to_node [MAX_MP_BUSSES]; |
| 48 | int mp_bus_id_to_local [MAX_MP_BUSSES]; |
| 49 | int quad_local_to_mp_bus_id [NR_CPUS/4][4]; |
| 50 | int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 }; |
| 51 | static int mp_current_pci_id; |
| 52 | |
| 53 | /* I/O APIC entries */ |
| 54 | struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; |
| 55 | |
| 56 | /* # of MP IRQ source entries */ |
| 57 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
| 58 | |
| 59 | /* MP IRQ source entries */ |
| 60 | int mp_irq_entries; |
| 61 | |
| 62 | int nr_ioapics; |
| 63 | |
| 64 | int pic_mode; |
| 65 | unsigned long mp_lapic_addr; |
| 66 | |
Venkatesh Pallipadi | 911a62d | 2005-09-03 15:56:31 -0700 | [diff] [blame] | 67 | unsigned int def_to_bigsmp = 0; |
| 68 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | /* Processor that is doing the boot up */ |
| 70 | unsigned int boot_cpu_physical_apicid = -1U; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | /* Internal processor count */ |
Natalie Protasevich | 9f40a72 | 2005-10-30 14:59:32 -0800 | [diff] [blame] | 72 | static unsigned int __devinitdata num_processors; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | |
| 74 | /* Bitmask of physically existing CPUs */ |
| 75 | physid_mask_t phys_cpu_present_map; |
| 76 | |
| 77 | u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID }; |
| 78 | |
| 79 | /* |
| 80 | * Intel MP BIOS table parsing routines: |
| 81 | */ |
| 82 | |
| 83 | |
| 84 | /* |
| 85 | * Checksum an MP configuration block. |
| 86 | */ |
| 87 | |
| 88 | static int __init mpf_checksum(unsigned char *mp, int len) |
| 89 | { |
| 90 | int sum = 0; |
| 91 | |
| 92 | while (len--) |
| 93 | sum += *mp++; |
| 94 | |
| 95 | return sum & 0xFF; |
| 96 | } |
| 97 | |
| 98 | /* |
| 99 | * Have to match translation table entries to main table entries by counter |
| 100 | * hence the mpc_record variable .... can't see a less disgusting way of |
| 101 | * doing this .... |
| 102 | */ |
| 103 | |
| 104 | static int mpc_record; |
| 105 | static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata; |
| 106 | |
| 107 | #ifdef CONFIG_X86_NUMAQ |
| 108 | static int MP_valid_apicid(int apicid, int version) |
| 109 | { |
| 110 | return hweight_long(apicid & 0xf) == 1 && (apicid >> 4) != 0xf; |
| 111 | } |
| 112 | #else |
| 113 | static int MP_valid_apicid(int apicid, int version) |
| 114 | { |
| 115 | if (version >= 0x14) |
| 116 | return apicid < 0xff; |
| 117 | else |
| 118 | return apicid < 0xf; |
| 119 | } |
| 120 | #endif |
| 121 | |
Natalie Protasevich | 9f40a72 | 2005-10-30 14:59:32 -0800 | [diff] [blame] | 122 | static void __devinit MP_processor_info (struct mpc_config_processor *m) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 123 | { |
Andrew Morton | 1299232 | 2005-09-09 13:01:21 -0700 | [diff] [blame] | 124 | int ver, apicid; |
| 125 | physid_mask_t phys_cpu; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | |
| 127 | if (!(m->mpc_cpuflag & CPU_ENABLED)) |
| 128 | return; |
| 129 | |
| 130 | apicid = mpc_apic_id(m, translation_table[mpc_record]); |
| 131 | |
| 132 | if (m->mpc_featureflag&(1<<0)) |
| 133 | Dprintk(" Floating point unit present.\n"); |
| 134 | if (m->mpc_featureflag&(1<<7)) |
| 135 | Dprintk(" Machine Exception supported.\n"); |
| 136 | if (m->mpc_featureflag&(1<<8)) |
| 137 | Dprintk(" 64 bit compare & exchange supported.\n"); |
| 138 | if (m->mpc_featureflag&(1<<9)) |
| 139 | Dprintk(" Internal APIC present.\n"); |
| 140 | if (m->mpc_featureflag&(1<<11)) |
| 141 | Dprintk(" SEP present.\n"); |
| 142 | if (m->mpc_featureflag&(1<<12)) |
| 143 | Dprintk(" MTRR present.\n"); |
| 144 | if (m->mpc_featureflag&(1<<13)) |
| 145 | Dprintk(" PGE present.\n"); |
| 146 | if (m->mpc_featureflag&(1<<14)) |
| 147 | Dprintk(" MCA present.\n"); |
| 148 | if (m->mpc_featureflag&(1<<15)) |
| 149 | Dprintk(" CMOV present.\n"); |
| 150 | if (m->mpc_featureflag&(1<<16)) |
| 151 | Dprintk(" PAT present.\n"); |
| 152 | if (m->mpc_featureflag&(1<<17)) |
| 153 | Dprintk(" PSE present.\n"); |
| 154 | if (m->mpc_featureflag&(1<<18)) |
| 155 | Dprintk(" PSN present.\n"); |
| 156 | if (m->mpc_featureflag&(1<<19)) |
| 157 | Dprintk(" Cache Line Flush Instruction present.\n"); |
| 158 | /* 20 Reserved */ |
| 159 | if (m->mpc_featureflag&(1<<21)) |
| 160 | Dprintk(" Debug Trace and EMON Store present.\n"); |
| 161 | if (m->mpc_featureflag&(1<<22)) |
| 162 | Dprintk(" ACPI Thermal Throttle Registers present.\n"); |
| 163 | if (m->mpc_featureflag&(1<<23)) |
| 164 | Dprintk(" MMX present.\n"); |
| 165 | if (m->mpc_featureflag&(1<<24)) |
| 166 | Dprintk(" FXSR present.\n"); |
| 167 | if (m->mpc_featureflag&(1<<25)) |
| 168 | Dprintk(" XMM present.\n"); |
| 169 | if (m->mpc_featureflag&(1<<26)) |
| 170 | Dprintk(" Willamette New Instructions present.\n"); |
| 171 | if (m->mpc_featureflag&(1<<27)) |
| 172 | Dprintk(" Self Snoop present.\n"); |
| 173 | if (m->mpc_featureflag&(1<<28)) |
| 174 | Dprintk(" HT present.\n"); |
| 175 | if (m->mpc_featureflag&(1<<29)) |
| 176 | Dprintk(" Thermal Monitor present.\n"); |
| 177 | /* 30, 31 Reserved */ |
| 178 | |
| 179 | |
| 180 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
| 181 | Dprintk(" Bootup CPU\n"); |
| 182 | boot_cpu_physical_apicid = m->mpc_apicid; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 183 | } |
| 184 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 185 | ver = m->mpc_apicver; |
| 186 | |
| 187 | if (!MP_valid_apicid(apicid, ver)) { |
| 188 | printk(KERN_WARNING "Processor #%d INVALID. (Max ID: %d).\n", |
| 189 | m->mpc_apicid, MAX_APICS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 190 | return; |
| 191 | } |
| 192 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | /* |
| 194 | * Validate version |
| 195 | */ |
| 196 | if (ver == 0x0) { |
Andrew Morton | 1299232 | 2005-09-09 13:01:21 -0700 | [diff] [blame] | 197 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " |
| 198 | "fixing up to 0x10. (tell your hw vendor)\n", |
| 199 | m->mpc_apicid); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | ver = 0x10; |
| 201 | } |
| 202 | apic_version[m->mpc_apicid] = ver; |
Eric W. Biederman | 6c180d9 | 2005-10-30 14:59:47 -0800 | [diff] [blame] | 203 | |
| 204 | phys_cpu = apicid_to_cpu_present(apicid); |
| 205 | physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu); |
| 206 | |
| 207 | if (num_processors >= NR_CPUS) { |
| 208 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." |
| 209 | " Processor ignored.\n", NR_CPUS); |
| 210 | return; |
| 211 | } |
| 212 | |
| 213 | if (num_processors >= maxcpus) { |
| 214 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." |
| 215 | " Processor ignored.\n", maxcpus); |
| 216 | return; |
| 217 | } |
| 218 | |
| 219 | cpu_set(num_processors, cpu_possible_map); |
| 220 | num_processors++; |
| 221 | |
Venkatesh Pallipadi | 911a62d | 2005-09-03 15:56:31 -0700 | [diff] [blame] | 222 | if ((num_processors > 8) && |
Andi Kleen | d716916 | 2005-11-20 18:49:05 +0100 | [diff] [blame] | 223 | ((APIC_XAPIC(ver) && |
| 224 | (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)) || |
| 225 | (boot_cpu_data.x86_vendor == X86_VENDOR_AMD))) |
Venkatesh Pallipadi | 911a62d | 2005-09-03 15:56:31 -0700 | [diff] [blame] | 226 | def_to_bigsmp = 1; |
| 227 | else |
| 228 | def_to_bigsmp = 0; |
| 229 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 230 | bios_cpu_apicid[num_processors - 1] = m->mpc_apicid; |
| 231 | } |
| 232 | |
| 233 | static void __init MP_bus_info (struct mpc_config_bus *m) |
| 234 | { |
| 235 | char str[7]; |
| 236 | |
| 237 | memcpy(str, m->mpc_bustype, 6); |
| 238 | str[6] = 0; |
| 239 | |
| 240 | mpc_oem_bus_info(m, str, translation_table[mpc_record]); |
| 241 | |
| 242 | if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) { |
| 243 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA; |
| 244 | } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) { |
| 245 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA; |
| 246 | } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) { |
| 247 | mpc_oem_pci_bus(m, translation_table[mpc_record]); |
| 248 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI; |
| 249 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
| 250 | mp_current_pci_id++; |
| 251 | } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) { |
| 252 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA; |
| 253 | } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) { |
| 254 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98; |
| 255 | } else { |
| 256 | printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str); |
| 257 | } |
| 258 | } |
| 259 | |
| 260 | static void __init MP_ioapic_info (struct mpc_config_ioapic *m) |
| 261 | { |
| 262 | if (!(m->mpc_flags & MPC_APIC_USABLE)) |
| 263 | return; |
| 264 | |
| 265 | printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n", |
| 266 | m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr); |
| 267 | if (nr_ioapics >= MAX_IO_APICS) { |
| 268 | printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n", |
| 269 | MAX_IO_APICS, nr_ioapics); |
| 270 | panic("Recompile kernel with bigger MAX_IO_APICS!.\n"); |
| 271 | } |
| 272 | if (!m->mpc_apicaddr) { |
| 273 | printk(KERN_ERR "WARNING: bogus zero I/O APIC address" |
| 274 | " found in MP table, skipping!\n"); |
| 275 | return; |
| 276 | } |
| 277 | mp_ioapics[nr_ioapics] = *m; |
| 278 | nr_ioapics++; |
| 279 | } |
| 280 | |
| 281 | static void __init MP_intsrc_info (struct mpc_config_intsrc *m) |
| 282 | { |
| 283 | mp_irqs [mp_irq_entries] = *m; |
| 284 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," |
| 285 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", |
| 286 | m->mpc_irqtype, m->mpc_irqflag & 3, |
| 287 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, |
| 288 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); |
| 289 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
| 290 | panic("Max # of irq sources exceeded!!\n"); |
| 291 | } |
| 292 | |
| 293 | static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m) |
| 294 | { |
| 295 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," |
| 296 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", |
| 297 | m->mpc_irqtype, m->mpc_irqflag & 3, |
| 298 | (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid, |
| 299 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); |
| 300 | /* |
| 301 | * Well it seems all SMP boards in existence |
| 302 | * use ExtINT/LVT1 == LINT0 and |
| 303 | * NMI/LVT2 == LINT1 - the following check |
| 304 | * will show us if this assumptions is false. |
| 305 | * Until then we do not have to add baggage. |
| 306 | */ |
| 307 | if ((m->mpc_irqtype == mp_ExtINT) && |
| 308 | (m->mpc_destapiclint != 0)) |
| 309 | BUG(); |
| 310 | if ((m->mpc_irqtype == mp_NMI) && |
| 311 | (m->mpc_destapiclint != 1)) |
| 312 | BUG(); |
| 313 | } |
| 314 | |
| 315 | #ifdef CONFIG_X86_NUMAQ |
| 316 | static void __init MP_translation_info (struct mpc_config_translation *m) |
| 317 | { |
| 318 | printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local); |
| 319 | |
| 320 | if (mpc_record >= MAX_MPC_ENTRY) |
| 321 | printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n"); |
| 322 | else |
| 323 | translation_table[mpc_record] = m; /* stash this for later */ |
| 324 | if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad)) |
| 325 | node_set_online(m->trans_quad); |
| 326 | } |
| 327 | |
| 328 | /* |
| 329 | * Read/parse the MPC oem tables |
| 330 | */ |
| 331 | |
| 332 | static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \ |
| 333 | unsigned short oemsize) |
| 334 | { |
| 335 | int count = sizeof (*oemtable); /* the header size */ |
| 336 | unsigned char *oemptr = ((unsigned char *)oemtable)+count; |
| 337 | |
| 338 | mpc_record = 0; |
| 339 | printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable); |
| 340 | if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4)) |
| 341 | { |
| 342 | printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n", |
| 343 | oemtable->oem_signature[0], |
| 344 | oemtable->oem_signature[1], |
| 345 | oemtable->oem_signature[2], |
| 346 | oemtable->oem_signature[3]); |
| 347 | return; |
| 348 | } |
| 349 | if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length)) |
| 350 | { |
| 351 | printk(KERN_WARNING "SMP oem mptable: checksum error!\n"); |
| 352 | return; |
| 353 | } |
| 354 | while (count < oemtable->oem_length) { |
| 355 | switch (*oemptr) { |
| 356 | case MP_TRANSLATION: |
| 357 | { |
| 358 | struct mpc_config_translation *m= |
| 359 | (struct mpc_config_translation *)oemptr; |
| 360 | MP_translation_info(m); |
| 361 | oemptr += sizeof(*m); |
| 362 | count += sizeof(*m); |
| 363 | ++mpc_record; |
| 364 | break; |
| 365 | } |
| 366 | default: |
| 367 | { |
| 368 | printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr); |
| 369 | return; |
| 370 | } |
| 371 | } |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | static inline void mps_oem_check(struct mp_config_table *mpc, char *oem, |
| 376 | char *productid) |
| 377 | { |
| 378 | if (strncmp(oem, "IBM NUMA", 8)) |
| 379 | printk("Warning! May not be a NUMA-Q system!\n"); |
| 380 | if (mpc->mpc_oemptr) |
| 381 | smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr, |
| 382 | mpc->mpc_oemsize); |
| 383 | } |
| 384 | #endif /* CONFIG_X86_NUMAQ */ |
| 385 | |
| 386 | /* |
| 387 | * Read/parse the MPC |
| 388 | */ |
| 389 | |
| 390 | static int __init smp_read_mpc(struct mp_config_table *mpc) |
| 391 | { |
| 392 | char str[16]; |
| 393 | char oem[10]; |
| 394 | int count=sizeof(*mpc); |
| 395 | unsigned char *mpt=((unsigned char *)mpc)+count; |
| 396 | |
| 397 | if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) { |
| 398 | printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n", |
| 399 | *(u32 *)mpc->mpc_signature); |
| 400 | return 0; |
| 401 | } |
| 402 | if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) { |
| 403 | printk(KERN_ERR "SMP mptable: checksum error!\n"); |
| 404 | return 0; |
| 405 | } |
| 406 | if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) { |
| 407 | printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n", |
| 408 | mpc->mpc_spec); |
| 409 | return 0; |
| 410 | } |
| 411 | if (!mpc->mpc_lapic) { |
| 412 | printk(KERN_ERR "SMP mptable: null local APIC address!\n"); |
| 413 | return 0; |
| 414 | } |
| 415 | memcpy(oem,mpc->mpc_oem,8); |
| 416 | oem[8]=0; |
| 417 | printk(KERN_INFO "OEM ID: %s ",oem); |
| 418 | |
| 419 | memcpy(str,mpc->mpc_productid,12); |
| 420 | str[12]=0; |
| 421 | printk("Product ID: %s ",str); |
| 422 | |
| 423 | mps_oem_check(mpc, oem, str); |
| 424 | |
| 425 | printk("APIC at: 0x%lX\n",mpc->mpc_lapic); |
| 426 | |
| 427 | /* |
| 428 | * Save the local APIC address (it might be non-default) -- but only |
| 429 | * if we're not using ACPI. |
| 430 | */ |
| 431 | if (!acpi_lapic) |
| 432 | mp_lapic_addr = mpc->mpc_lapic; |
| 433 | |
| 434 | /* |
| 435 | * Now process the configuration blocks. |
| 436 | */ |
| 437 | mpc_record = 0; |
| 438 | while (count < mpc->mpc_length) { |
| 439 | switch(*mpt) { |
| 440 | case MP_PROCESSOR: |
| 441 | { |
| 442 | struct mpc_config_processor *m= |
| 443 | (struct mpc_config_processor *)mpt; |
| 444 | /* ACPI may have already provided this data */ |
| 445 | if (!acpi_lapic) |
| 446 | MP_processor_info(m); |
| 447 | mpt += sizeof(*m); |
| 448 | count += sizeof(*m); |
| 449 | break; |
| 450 | } |
| 451 | case MP_BUS: |
| 452 | { |
| 453 | struct mpc_config_bus *m= |
| 454 | (struct mpc_config_bus *)mpt; |
| 455 | MP_bus_info(m); |
| 456 | mpt += sizeof(*m); |
| 457 | count += sizeof(*m); |
| 458 | break; |
| 459 | } |
| 460 | case MP_IOAPIC: |
| 461 | { |
| 462 | struct mpc_config_ioapic *m= |
| 463 | (struct mpc_config_ioapic *)mpt; |
| 464 | MP_ioapic_info(m); |
| 465 | mpt+=sizeof(*m); |
| 466 | count+=sizeof(*m); |
| 467 | break; |
| 468 | } |
| 469 | case MP_INTSRC: |
| 470 | { |
| 471 | struct mpc_config_intsrc *m= |
| 472 | (struct mpc_config_intsrc *)mpt; |
| 473 | |
| 474 | MP_intsrc_info(m); |
| 475 | mpt+=sizeof(*m); |
| 476 | count+=sizeof(*m); |
| 477 | break; |
| 478 | } |
| 479 | case MP_LINTSRC: |
| 480 | { |
| 481 | struct mpc_config_lintsrc *m= |
| 482 | (struct mpc_config_lintsrc *)mpt; |
| 483 | MP_lintsrc_info(m); |
| 484 | mpt+=sizeof(*m); |
| 485 | count+=sizeof(*m); |
| 486 | break; |
| 487 | } |
| 488 | default: |
| 489 | { |
| 490 | count = mpc->mpc_length; |
| 491 | break; |
| 492 | } |
| 493 | } |
| 494 | ++mpc_record; |
| 495 | } |
| 496 | clustered_apic_check(); |
| 497 | if (!num_processors) |
| 498 | printk(KERN_ERR "SMP mptable: no processors registered!\n"); |
| 499 | return num_processors; |
| 500 | } |
| 501 | |
| 502 | static int __init ELCR_trigger(unsigned int irq) |
| 503 | { |
| 504 | unsigned int port; |
| 505 | |
| 506 | port = 0x4d0 + (irq >> 3); |
| 507 | return (inb(port) >> (irq & 7)) & 1; |
| 508 | } |
| 509 | |
| 510 | static void __init construct_default_ioirq_mptable(int mpc_default_type) |
| 511 | { |
| 512 | struct mpc_config_intsrc intsrc; |
| 513 | int i; |
| 514 | int ELCR_fallback = 0; |
| 515 | |
| 516 | intsrc.mpc_type = MP_INTSRC; |
| 517 | intsrc.mpc_irqflag = 0; /* conforming */ |
| 518 | intsrc.mpc_srcbus = 0; |
| 519 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; |
| 520 | |
| 521 | intsrc.mpc_irqtype = mp_INT; |
| 522 | |
| 523 | /* |
| 524 | * If true, we have an ISA/PCI system with no IRQ entries |
| 525 | * in the MP table. To prevent the PCI interrupts from being set up |
| 526 | * incorrectly, we try to use the ELCR. The sanity check to see if |
| 527 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can |
| 528 | * never be level sensitive, so we simply see if the ELCR agrees. |
| 529 | * If it does, we assume it's valid. |
| 530 | */ |
| 531 | if (mpc_default_type == 5) { |
| 532 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); |
| 533 | |
| 534 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13)) |
| 535 | printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n"); |
| 536 | else { |
| 537 | printk(KERN_INFO "Using ELCR to identify PCI interrupts\n"); |
| 538 | ELCR_fallback = 1; |
| 539 | } |
| 540 | } |
| 541 | |
| 542 | for (i = 0; i < 16; i++) { |
| 543 | switch (mpc_default_type) { |
| 544 | case 2: |
| 545 | if (i == 0 || i == 13) |
| 546 | continue; /* IRQ0 & IRQ13 not connected */ |
| 547 | /* fall through */ |
| 548 | default: |
| 549 | if (i == 2) |
| 550 | continue; /* IRQ2 is never connected */ |
| 551 | } |
| 552 | |
| 553 | if (ELCR_fallback) { |
| 554 | /* |
| 555 | * If the ELCR indicates a level-sensitive interrupt, we |
| 556 | * copy that information over to the MP table in the |
| 557 | * irqflag field (level sensitive, active high polarity). |
| 558 | */ |
| 559 | if (ELCR_trigger(i)) |
| 560 | intsrc.mpc_irqflag = 13; |
| 561 | else |
| 562 | intsrc.mpc_irqflag = 0; |
| 563 | } |
| 564 | |
| 565 | intsrc.mpc_srcbusirq = i; |
| 566 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ |
| 567 | MP_intsrc_info(&intsrc); |
| 568 | } |
| 569 | |
| 570 | intsrc.mpc_irqtype = mp_ExtINT; |
| 571 | intsrc.mpc_srcbusirq = 0; |
| 572 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ |
| 573 | MP_intsrc_info(&intsrc); |
| 574 | } |
| 575 | |
| 576 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) |
| 577 | { |
| 578 | struct mpc_config_processor processor; |
| 579 | struct mpc_config_bus bus; |
| 580 | struct mpc_config_ioapic ioapic; |
| 581 | struct mpc_config_lintsrc lintsrc; |
| 582 | int linttypes[2] = { mp_ExtINT, mp_NMI }; |
| 583 | int i; |
| 584 | |
| 585 | /* |
| 586 | * local APIC has default address |
| 587 | */ |
| 588 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
| 589 | |
| 590 | /* |
| 591 | * 2 CPUs, numbered 0 & 1. |
| 592 | */ |
| 593 | processor.mpc_type = MP_PROCESSOR; |
| 594 | /* Either an integrated APIC or a discrete 82489DX. */ |
| 595 | processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; |
| 596 | processor.mpc_cpuflag = CPU_ENABLED; |
| 597 | processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | |
| 598 | (boot_cpu_data.x86_model << 4) | |
| 599 | boot_cpu_data.x86_mask; |
| 600 | processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; |
| 601 | processor.mpc_reserved[0] = 0; |
| 602 | processor.mpc_reserved[1] = 0; |
| 603 | for (i = 0; i < 2; i++) { |
| 604 | processor.mpc_apicid = i; |
| 605 | MP_processor_info(&processor); |
| 606 | } |
| 607 | |
| 608 | bus.mpc_type = MP_BUS; |
| 609 | bus.mpc_busid = 0; |
| 610 | switch (mpc_default_type) { |
| 611 | default: |
| 612 | printk("???\n"); |
| 613 | printk(KERN_ERR "Unknown standard configuration %d\n", |
| 614 | mpc_default_type); |
| 615 | /* fall through */ |
| 616 | case 1: |
| 617 | case 5: |
| 618 | memcpy(bus.mpc_bustype, "ISA ", 6); |
| 619 | break; |
| 620 | case 2: |
| 621 | case 6: |
| 622 | case 3: |
| 623 | memcpy(bus.mpc_bustype, "EISA ", 6); |
| 624 | break; |
| 625 | case 4: |
| 626 | case 7: |
| 627 | memcpy(bus.mpc_bustype, "MCA ", 6); |
| 628 | } |
| 629 | MP_bus_info(&bus); |
| 630 | if (mpc_default_type > 4) { |
| 631 | bus.mpc_busid = 1; |
| 632 | memcpy(bus.mpc_bustype, "PCI ", 6); |
| 633 | MP_bus_info(&bus); |
| 634 | } |
| 635 | |
| 636 | ioapic.mpc_type = MP_IOAPIC; |
| 637 | ioapic.mpc_apicid = 2; |
| 638 | ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; |
| 639 | ioapic.mpc_flags = MPC_APIC_USABLE; |
| 640 | ioapic.mpc_apicaddr = 0xFEC00000; |
| 641 | MP_ioapic_info(&ioapic); |
| 642 | |
| 643 | /* |
| 644 | * We set up most of the low 16 IO-APIC pins according to MPS rules. |
| 645 | */ |
| 646 | construct_default_ioirq_mptable(mpc_default_type); |
| 647 | |
| 648 | lintsrc.mpc_type = MP_LINTSRC; |
| 649 | lintsrc.mpc_irqflag = 0; /* conforming */ |
| 650 | lintsrc.mpc_srcbusid = 0; |
| 651 | lintsrc.mpc_srcbusirq = 0; |
| 652 | lintsrc.mpc_destapic = MP_APIC_ALL; |
| 653 | for (i = 0; i < 2; i++) { |
| 654 | lintsrc.mpc_irqtype = linttypes[i]; |
| 655 | lintsrc.mpc_destapiclint = i; |
| 656 | MP_lintsrc_info(&lintsrc); |
| 657 | } |
| 658 | } |
| 659 | |
| 660 | static struct intel_mp_floating *mpf_found; |
| 661 | |
| 662 | /* |
| 663 | * Scan the memory blocks for an SMP configuration block. |
| 664 | */ |
| 665 | void __init get_smp_config (void) |
| 666 | { |
| 667 | struct intel_mp_floating *mpf = mpf_found; |
| 668 | |
| 669 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 670 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
| 671 | * processors, where MPS only supports physical. |
| 672 | */ |
| 673 | if (acpi_lapic && acpi_ioapic) { |
| 674 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n"); |
| 675 | return; |
| 676 | } |
| 677 | else if (acpi_lapic) |
| 678 | printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n"); |
| 679 | |
| 680 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification); |
| 681 | if (mpf->mpf_feature2 & (1<<7)) { |
| 682 | printk(KERN_INFO " IMCR and PIC compatibility mode.\n"); |
| 683 | pic_mode = 1; |
| 684 | } else { |
| 685 | printk(KERN_INFO " Virtual Wire compatibility mode.\n"); |
| 686 | pic_mode = 0; |
| 687 | } |
| 688 | |
| 689 | /* |
| 690 | * Now see if we need to read further. |
| 691 | */ |
| 692 | if (mpf->mpf_feature1 != 0) { |
| 693 | |
| 694 | printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1); |
| 695 | construct_default_ISA_mptable(mpf->mpf_feature1); |
| 696 | |
| 697 | } else if (mpf->mpf_physptr) { |
| 698 | |
| 699 | /* |
| 700 | * Read the physical hardware table. Anything here will |
| 701 | * override the defaults. |
| 702 | */ |
| 703 | if (!smp_read_mpc((void *)mpf->mpf_physptr)) { |
| 704 | smp_found_config = 0; |
| 705 | printk(KERN_ERR "BIOS bug, MP table errors detected!...\n"); |
| 706 | printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n"); |
| 707 | return; |
| 708 | } |
| 709 | /* |
| 710 | * If there are no explicit MP IRQ entries, then we are |
| 711 | * broken. We set up most of the low 16 IO-APIC pins to |
| 712 | * ISA defaults and hope it will work. |
| 713 | */ |
| 714 | if (!mp_irq_entries) { |
| 715 | struct mpc_config_bus bus; |
| 716 | |
| 717 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); |
| 718 | |
| 719 | bus.mpc_type = MP_BUS; |
| 720 | bus.mpc_busid = 0; |
| 721 | memcpy(bus.mpc_bustype, "ISA ", 6); |
| 722 | MP_bus_info(&bus); |
| 723 | |
| 724 | construct_default_ioirq_mptable(0); |
| 725 | } |
| 726 | |
| 727 | } else |
| 728 | BUG(); |
| 729 | |
| 730 | printk(KERN_INFO "Processors: %d\n", num_processors); |
| 731 | /* |
| 732 | * Only use the first configuration found. |
| 733 | */ |
| 734 | } |
| 735 | |
| 736 | static int __init smp_scan_config (unsigned long base, unsigned long length) |
| 737 | { |
| 738 | unsigned long *bp = phys_to_virt(base); |
| 739 | struct intel_mp_floating *mpf; |
| 740 | |
| 741 | Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length); |
| 742 | if (sizeof(*mpf) != 16) |
| 743 | printk("Error: MPF size\n"); |
| 744 | |
| 745 | while (length > 0) { |
| 746 | mpf = (struct intel_mp_floating *)bp; |
| 747 | if ((*bp == SMP_MAGIC_IDENT) && |
| 748 | (mpf->mpf_length == 1) && |
| 749 | !mpf_checksum((unsigned char *)bp, 16) && |
| 750 | ((mpf->mpf_specification == 1) |
| 751 | || (mpf->mpf_specification == 4)) ) { |
| 752 | |
| 753 | smp_found_config = 1; |
| 754 | printk(KERN_INFO "found SMP MP-table at %08lx\n", |
| 755 | virt_to_phys(mpf)); |
| 756 | reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE); |
| 757 | if (mpf->mpf_physptr) { |
| 758 | /* |
| 759 | * We cannot access to MPC table to compute |
| 760 | * table size yet, as only few megabytes from |
| 761 | * the bottom is mapped now. |
| 762 | * PC-9800's MPC table places on the very last |
| 763 | * of physical memory; so that simply reserving |
| 764 | * PAGE_SIZE from mpg->mpf_physptr yields BUG() |
| 765 | * in reserve_bootmem. |
| 766 | */ |
| 767 | unsigned long size = PAGE_SIZE; |
| 768 | unsigned long end = max_low_pfn * PAGE_SIZE; |
| 769 | if (mpf->mpf_physptr + size > end) |
| 770 | size = end - mpf->mpf_physptr; |
| 771 | reserve_bootmem(mpf->mpf_physptr, size); |
| 772 | } |
| 773 | |
| 774 | mpf_found = mpf; |
| 775 | return 1; |
| 776 | } |
| 777 | bp += 4; |
| 778 | length -= 16; |
| 779 | } |
| 780 | return 0; |
| 781 | } |
| 782 | |
| 783 | void __init find_smp_config (void) |
| 784 | { |
| 785 | unsigned int address; |
| 786 | |
| 787 | /* |
| 788 | * FIXME: Linux assumes you have 640K of base ram.. |
| 789 | * this continues the error... |
| 790 | * |
| 791 | * 1) Scan the bottom 1K for a signature |
| 792 | * 2) Scan the top 1K of base RAM |
| 793 | * 3) Scan the 64K of bios |
| 794 | */ |
| 795 | if (smp_scan_config(0x0,0x400) || |
| 796 | smp_scan_config(639*0x400,0x400) || |
| 797 | smp_scan_config(0xF0000,0x10000)) |
| 798 | return; |
| 799 | /* |
| 800 | * If it is an SMP machine we should know now, unless the |
| 801 | * configuration is in an EISA/MCA bus machine with an |
| 802 | * extended bios data area. |
| 803 | * |
| 804 | * there is a real-mode segmented pointer pointing to the |
| 805 | * 4K EBDA area at 0x40E, calculate and scan it here. |
| 806 | * |
| 807 | * NOTE! There are Linux loaders that will corrupt the EBDA |
| 808 | * area, and as such this kind of SMP config may be less |
| 809 | * trustworthy, simply because the SMP table may have been |
| 810 | * stomped on during early boot. These loaders are buggy and |
| 811 | * should be fixed. |
| 812 | * |
| 813 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. |
| 814 | */ |
| 815 | |
| 816 | address = get_bios_ebda(); |
| 817 | if (address) |
| 818 | smp_scan_config(address, 0x400); |
| 819 | } |
| 820 | |
| 821 | /* -------------------------------------------------------------------------- |
| 822 | ACPI-based MP Configuration |
| 823 | -------------------------------------------------------------------------- */ |
| 824 | |
Len Brown | 888ba6c | 2005-08-24 12:07:20 -0400 | [diff] [blame] | 825 | #ifdef CONFIG_ACPI |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 826 | |
| 827 | void __init mp_register_lapic_address ( |
| 828 | u64 address) |
| 829 | { |
| 830 | mp_lapic_addr = (unsigned long) address; |
| 831 | |
| 832 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); |
| 833 | |
| 834 | if (boot_cpu_physical_apicid == -1U) |
| 835 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
| 836 | |
| 837 | Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid); |
| 838 | } |
| 839 | |
| 840 | |
Natalie Protasevich | 9f40a72 | 2005-10-30 14:59:32 -0800 | [diff] [blame] | 841 | void __devinit mp_register_lapic ( |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 842 | u8 id, |
| 843 | u8 enabled) |
| 844 | { |
| 845 | struct mpc_config_processor processor; |
| 846 | int boot_cpu = 0; |
| 847 | |
| 848 | if (MAX_APICS - id <= 0) { |
| 849 | printk(KERN_WARNING "Processor #%d invalid (max %d)\n", |
| 850 | id, MAX_APICS); |
| 851 | return; |
| 852 | } |
| 853 | |
| 854 | if (id == boot_cpu_physical_apicid) |
| 855 | boot_cpu = 1; |
| 856 | |
| 857 | processor.mpc_type = MP_PROCESSOR; |
| 858 | processor.mpc_apicid = id; |
| 859 | processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 860 | processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0); |
| 861 | processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0); |
| 862 | processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | |
| 863 | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; |
| 864 | processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; |
| 865 | processor.mpc_reserved[0] = 0; |
| 866 | processor.mpc_reserved[1] = 0; |
| 867 | |
| 868 | MP_processor_info(&processor); |
| 869 | } |
| 870 | |
Len Brown | 8466361 | 2005-08-24 12:09:07 -0400 | [diff] [blame] | 871 | #ifdef CONFIG_X86_IO_APIC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 872 | |
| 873 | #define MP_ISA_BUS 0 |
| 874 | #define MP_MAX_IOAPIC_PIN 127 |
| 875 | |
| 876 | static struct mp_ioapic_routing { |
| 877 | int apic_id; |
| 878 | int gsi_base; |
| 879 | int gsi_end; |
| 880 | u32 pin_programmed[4]; |
| 881 | } mp_ioapic_routing[MAX_IO_APICS]; |
| 882 | |
| 883 | |
| 884 | static int mp_find_ioapic ( |
| 885 | int gsi) |
| 886 | { |
| 887 | int i = 0; |
| 888 | |
| 889 | /* Find the IOAPIC that manages this GSI. */ |
| 890 | for (i = 0; i < nr_ioapics; i++) { |
| 891 | if ((gsi >= mp_ioapic_routing[i].gsi_base) |
| 892 | && (gsi <= mp_ioapic_routing[i].gsi_end)) |
| 893 | return i; |
| 894 | } |
| 895 | |
| 896 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
| 897 | |
| 898 | return -1; |
| 899 | } |
| 900 | |
| 901 | |
| 902 | void __init mp_register_ioapic ( |
| 903 | u8 id, |
| 904 | u32 address, |
| 905 | u32 gsi_base) |
| 906 | { |
| 907 | int idx = 0; |
| 908 | |
| 909 | if (nr_ioapics >= MAX_IO_APICS) { |
| 910 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " |
| 911 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); |
| 912 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); |
| 913 | } |
| 914 | if (!address) { |
| 915 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" |
| 916 | " found in MADT table, skipping!\n"); |
| 917 | return; |
| 918 | } |
| 919 | |
| 920 | idx = nr_ioapics++; |
| 921 | |
| 922 | mp_ioapics[idx].mpc_type = MP_IOAPIC; |
| 923 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; |
| 924 | mp_ioapics[idx].mpc_apicaddr = address; |
| 925 | |
| 926 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); |
Natalie Protasevich | ca05fea | 2005-06-23 00:08:22 -0700 | [diff] [blame] | 927 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 < 15)) |
| 928 | mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id); |
| 929 | else |
| 930 | mp_ioapics[idx].mpc_apicid = id; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 931 | mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx); |
| 932 | |
| 933 | /* |
| 934 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups |
| 935 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). |
| 936 | */ |
| 937 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; |
| 938 | mp_ioapic_routing[idx].gsi_base = gsi_base; |
| 939 | mp_ioapic_routing[idx].gsi_end = gsi_base + |
| 940 | io_apic_get_redir_entries(idx); |
| 941 | |
| 942 | printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, " |
| 943 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, |
| 944 | mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr, |
| 945 | mp_ioapic_routing[idx].gsi_base, |
| 946 | mp_ioapic_routing[idx].gsi_end); |
| 947 | |
| 948 | return; |
| 949 | } |
| 950 | |
| 951 | |
| 952 | void __init mp_override_legacy_irq ( |
| 953 | u8 bus_irq, |
| 954 | u8 polarity, |
| 955 | u8 trigger, |
| 956 | u32 gsi) |
| 957 | { |
| 958 | struct mpc_config_intsrc intsrc; |
| 959 | int ioapic = -1; |
| 960 | int pin = -1; |
| 961 | |
| 962 | /* |
| 963 | * Convert 'gsi' to 'ioapic.pin'. |
| 964 | */ |
| 965 | ioapic = mp_find_ioapic(gsi); |
| 966 | if (ioapic < 0) |
| 967 | return; |
| 968 | pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
| 969 | |
| 970 | /* |
| 971 | * TBD: This check is for faulty timer entries, where the override |
| 972 | * erroneously sets the trigger to level, resulting in a HUGE |
| 973 | * increase of timer interrupts! |
| 974 | */ |
| 975 | if ((bus_irq == 0) && (trigger == 3)) |
| 976 | trigger = 1; |
| 977 | |
| 978 | intsrc.mpc_type = MP_INTSRC; |
| 979 | intsrc.mpc_irqtype = mp_INT; |
| 980 | intsrc.mpc_irqflag = (trigger << 2) | polarity; |
| 981 | intsrc.mpc_srcbus = MP_ISA_BUS; |
| 982 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ |
| 983 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ |
| 984 | intsrc.mpc_dstirq = pin; /* INTIN# */ |
| 985 | |
| 986 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", |
| 987 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
| 988 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, |
| 989 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); |
| 990 | |
| 991 | mp_irqs[mp_irq_entries] = intsrc; |
| 992 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
| 993 | panic("Max # of irq sources exceeded!\n"); |
| 994 | |
| 995 | return; |
| 996 | } |
| 997 | |
| 998 | int es7000_plat; |
| 999 | |
| 1000 | void __init mp_config_acpi_legacy_irqs (void) |
| 1001 | { |
| 1002 | struct mpc_config_intsrc intsrc; |
| 1003 | int i = 0; |
| 1004 | int ioapic = -1; |
| 1005 | |
| 1006 | /* |
| 1007 | * Fabricate the legacy ISA bus (bus #31). |
| 1008 | */ |
| 1009 | mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA; |
| 1010 | Dprintk("Bus #%d is ISA\n", MP_ISA_BUS); |
| 1011 | |
| 1012 | /* |
| 1013 | * Older generations of ES7000 have no legacy identity mappings |
| 1014 | */ |
| 1015 | if (es7000_plat == 1) |
| 1016 | return; |
| 1017 | |
| 1018 | /* |
| 1019 | * Locate the IOAPIC that manages the ISA IRQs (0-15). |
| 1020 | */ |
| 1021 | ioapic = mp_find_ioapic(0); |
| 1022 | if (ioapic < 0) |
| 1023 | return; |
| 1024 | |
| 1025 | intsrc.mpc_type = MP_INTSRC; |
| 1026 | intsrc.mpc_irqflag = 0; /* Conforming */ |
| 1027 | intsrc.mpc_srcbus = MP_ISA_BUS; |
| 1028 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; |
| 1029 | |
| 1030 | /* |
| 1031 | * Use the default configuration for the IRQs 0-15. Unless |
| 1032 | * overriden by (MADT) interrupt source override entries. |
| 1033 | */ |
| 1034 | for (i = 0; i < 16; i++) { |
| 1035 | int idx; |
| 1036 | |
| 1037 | for (idx = 0; idx < mp_irq_entries; idx++) { |
| 1038 | struct mpc_config_intsrc *irq = mp_irqs + idx; |
| 1039 | |
| 1040 | /* Do we already have a mapping for this ISA IRQ? */ |
| 1041 | if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i) |
| 1042 | break; |
| 1043 | |
| 1044 | /* Do we already have a mapping for this IOAPIC pin */ |
| 1045 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && |
| 1046 | (irq->mpc_dstirq == i)) |
| 1047 | break; |
| 1048 | } |
| 1049 | |
| 1050 | if (idx != mp_irq_entries) { |
| 1051 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); |
| 1052 | continue; /* IRQ already used */ |
| 1053 | } |
| 1054 | |
| 1055 | intsrc.mpc_irqtype = mp_INT; |
| 1056 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ |
| 1057 | intsrc.mpc_dstirq = i; |
| 1058 | |
| 1059 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " |
| 1060 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
| 1061 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, |
| 1062 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, |
| 1063 | intsrc.mpc_dstirq); |
| 1064 | |
| 1065 | mp_irqs[mp_irq_entries] = intsrc; |
| 1066 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
| 1067 | panic("Max # of irq sources exceeded!\n"); |
| 1068 | } |
| 1069 | } |
| 1070 | |
Natalie Protasevich | c434b7a | 2005-06-23 00:08:29 -0700 | [diff] [blame] | 1071 | #define MAX_GSI_NUM 4096 |
| 1072 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1073 | int mp_register_gsi (u32 gsi, int edge_level, int active_high_low) |
| 1074 | { |
| 1075 | int ioapic = -1; |
| 1076 | int ioapic_pin = 0; |
| 1077 | int idx, bit = 0; |
Natalie Protasevich | c434b7a | 2005-06-23 00:08:29 -0700 | [diff] [blame] | 1078 | static int pci_irq = 16; |
| 1079 | /* |
| 1080 | * Mapping between Global System Interrups, which |
| 1081 | * represent all possible interrupts, and IRQs |
| 1082 | * assigned to actual devices. |
| 1083 | */ |
| 1084 | static int gsi_to_irq[MAX_GSI_NUM]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1085 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1086 | /* Don't set up the ACPI SCI because it's already set up */ |
| 1087 | if (acpi_fadt.sci_int == gsi) |
| 1088 | return gsi; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1089 | |
| 1090 | ioapic = mp_find_ioapic(gsi); |
| 1091 | if (ioapic < 0) { |
| 1092 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); |
| 1093 | return gsi; |
| 1094 | } |
| 1095 | |
| 1096 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
| 1097 | |
| 1098 | if (ioapic_renumber_irq) |
| 1099 | gsi = ioapic_renumber_irq(ioapic, gsi); |
| 1100 | |
| 1101 | /* |
| 1102 | * Avoid pin reprogramming. PRTs typically include entries |
| 1103 | * with redundant pin->gsi mappings (but unique PCI devices); |
| 1104 | * we only program the IOAPIC on the first. |
| 1105 | */ |
| 1106 | bit = ioapic_pin % 32; |
| 1107 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); |
| 1108 | if (idx > 3) { |
| 1109 | printk(KERN_ERR "Invalid reference to IOAPIC pin " |
| 1110 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, |
| 1111 | ioapic_pin); |
| 1112 | return gsi; |
| 1113 | } |
| 1114 | if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { |
| 1115 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", |
| 1116 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); |
Natalie Protasevich | c434b7a | 2005-06-23 00:08:29 -0700 | [diff] [blame] | 1117 | return gsi_to_irq[gsi]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1118 | } |
| 1119 | |
| 1120 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); |
| 1121 | |
Natalie Protasevich | c434b7a | 2005-06-23 00:08:29 -0700 | [diff] [blame] | 1122 | if (edge_level) { |
| 1123 | /* |
| 1124 | * For PCI devices assign IRQs in order, avoiding gaps |
| 1125 | * due to unused I/O APIC pins. |
| 1126 | */ |
| 1127 | int irq = gsi; |
| 1128 | if (gsi < MAX_GSI_NUM) { |
Natalie.Protasevich@unisys.com | e1afc3f | 2005-07-29 14:03:32 -0700 | [diff] [blame] | 1129 | if (gsi > 15) |
| 1130 | gsi = pci_irq++; |
Natalie.Protasevich@unisys.com | e1afc3f | 2005-07-29 14:03:32 -0700 | [diff] [blame] | 1131 | /* |
| 1132 | * Don't assign IRQ used by ACPI SCI |
| 1133 | */ |
| 1134 | if (gsi == acpi_fadt.sci_int) |
| 1135 | gsi = pci_irq++; |
Natalie Protasevich | c434b7a | 2005-06-23 00:08:29 -0700 | [diff] [blame] | 1136 | gsi_to_irq[irq] = gsi; |
| 1137 | } else { |
| 1138 | printk(KERN_ERR "GSI %u is too high\n", gsi); |
| 1139 | return gsi; |
| 1140 | } |
| 1141 | } |
| 1142 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1143 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, |
| 1144 | edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1, |
| 1145 | active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1); |
| 1146 | return gsi; |
| 1147 | } |
| 1148 | |
Len Brown | 8466361 | 2005-08-24 12:09:07 -0400 | [diff] [blame] | 1149 | #endif /* CONFIG_X86_IO_APIC */ |
Len Brown | 888ba6c | 2005-08-24 12:07:20 -0400 | [diff] [blame] | 1150 | #endif /* CONFIG_ACPI */ |