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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / fe489bf4505ae26d3c6d6a1f1d3064c2a9c5cd85 / . / arch / arm64 / kernel / asm-offsets.c
blob: 49c162c03b696c9f7f9501c666d093b98a27e8ab [file] [log] [blame]
Catalin Marinas0be73202012-03-05 11:49:26 +0000[diff] [blame]1/*
2 * Based on arch/arm/kernel/asm-offsets.c
3 *
4 * Copyright (C) 1995-2003 Russell King
5 * 2001-2002 Keith Owens
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/sched.h>
22#include <linux/mm.h>
23#include <linux/dma-mapping.h>
24#include <asm/thread_info.h>
25#include <asm/memory.h>
26#include <asm/cputable.h>
27#include <asm/vdso_datapage.h>
28#include <linux/kbuild.h>
29
30int main(void)
31{
32 DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
33 BLANK();
34 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
35 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
36 DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit));
37 DEFINE(TI_TASK, offsetof(struct thread_info, task));
38 DEFINE(TI_EXEC_DOMAIN, offsetof(struct thread_info, exec_domain));
39 DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
40 BLANK();
41 DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context));
42 BLANK();
43 DEFINE(S_X0, offsetof(struct pt_regs, regs[0]));
44 DEFINE(S_X1, offsetof(struct pt_regs, regs[1]));
45 DEFINE(S_X2, offsetof(struct pt_regs, regs[2]));
46 DEFINE(S_X3, offsetof(struct pt_regs, regs[3]));
47 DEFINE(S_X4, offsetof(struct pt_regs, regs[4]));
48 DEFINE(S_X5, offsetof(struct pt_regs, regs[5]));
49 DEFINE(S_X6, offsetof(struct pt_regs, regs[6]));
50 DEFINE(S_X7, offsetof(struct pt_regs, regs[7]));
51 DEFINE(S_LR, offsetof(struct pt_regs, regs[30]));
52 DEFINE(S_SP, offsetof(struct pt_regs, sp));
53#ifdef CONFIG_COMPAT
54 DEFINE(S_COMPAT_SP, offsetof(struct pt_regs, compat_sp));
55#endif
56 DEFINE(S_PSTATE, offsetof(struct pt_regs, pstate));
57 DEFINE(S_PC, offsetof(struct pt_regs, pc));
58 DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0));
59 DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno));
60 DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
61 BLANK();
62 DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id));
63 BLANK();
64 DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
65 DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
66 BLANK();
67 DEFINE(VM_EXEC, VM_EXEC);
68 BLANK();
69 DEFINE(PAGE_SZ, PAGE_SIZE);
70 BLANK();
71 DEFINE(CPU_INFO_SZ, sizeof(struct cpu_info));
72 DEFINE(CPU_INFO_SETUP, offsetof(struct cpu_info, cpu_setup));
73 BLANK();
74 DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
75 DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
76 DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
77 BLANK();
78 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
79 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
80 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
81 DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
82 DEFINE(CLOCK_MONOTONIC_COARSE,CLOCK_MONOTONIC_COARSE);
83 DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC);
84 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
85 BLANK();
86 DEFINE(VDSO_CS_CYCLE_LAST, offsetof(struct vdso_data, cs_cycle_last));
87 DEFINE(VDSO_XTIME_CLK_SEC, offsetof(struct vdso_data, xtime_clock_sec));
88 DEFINE(VDSO_XTIME_CLK_NSEC, offsetof(struct vdso_data, xtime_clock_nsec));
89 DEFINE(VDSO_XTIME_CRS_SEC, offsetof(struct vdso_data, xtime_coarse_sec));
90 DEFINE(VDSO_XTIME_CRS_NSEC, offsetof(struct vdso_data, xtime_coarse_nsec));
91 DEFINE(VDSO_WTM_CLK_SEC, offsetof(struct vdso_data, wtm_clock_sec));
92 DEFINE(VDSO_WTM_CLK_NSEC, offsetof(struct vdso_data, wtm_clock_nsec));
93 DEFINE(VDSO_TB_SEQ_COUNT, offsetof(struct vdso_data, tb_seq_count));
94 DEFINE(VDSO_CS_MULT, offsetof(struct vdso_data, cs_mult));
95 DEFINE(VDSO_CS_SHIFT, offsetof(struct vdso_data, cs_shift));
96 DEFINE(VDSO_TZ_MINWEST, offsetof(struct vdso_data, tz_minuteswest));
97 DEFINE(VDSO_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime));
98 DEFINE(VDSO_USE_SYSCALL, offsetof(struct vdso_data, use_syscall));
99 BLANK();
100 DEFINE(TVAL_TV_SEC, offsetof(struct timeval, tv_sec));
101 DEFINE(TVAL_TV_USEC, offsetof(struct timeval, tv_usec));
102 DEFINE(TSPEC_TV_SEC, offsetof(struct timespec, tv_sec));
103 DEFINE(TSPEC_TV_NSEC, offsetof(struct timespec, tv_nsec));
104 BLANK();
105 DEFINE(TZ_MINWEST, offsetof(struct timezone, tz_minuteswest));
106 DEFINE(TZ_DSTTIME, offsetof(struct timezone, tz_dsttime));
Marc Zyngier55c74012012-12-10 16:40:18 +0000[diff] [blame]107 BLANK();
108#ifdef CONFIG_KVM_ARM_HOST
109 DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt));
110 DEFINE(CPU_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs));
111 DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_regs, regs));
112 DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs));
113 DEFINE(CPU_SP_EL1, offsetof(struct kvm_regs, sp_el1));
114 DEFINE(CPU_ELR_EL1, offsetof(struct kvm_regs, elr_el1));
115 DEFINE(CPU_SPSR, offsetof(struct kvm_regs, spsr));
116 DEFINE(CPU_SYSREGS, offsetof(struct kvm_cpu_context, sys_regs));
117 DEFINE(VCPU_ESR_EL2, offsetof(struct kvm_vcpu, arch.fault.esr_el2));
118 DEFINE(VCPU_FAR_EL2, offsetof(struct kvm_vcpu, arch.fault.far_el2));
119 DEFINE(VCPU_HPFAR_EL2, offsetof(struct kvm_vcpu, arch.fault.hpfar_el2));
120 DEFINE(VCPU_HCR_EL2, offsetof(struct kvm_vcpu, arch.hcr_el2));
121 DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines));
122 DEFINE(VCPU_HOST_CONTEXT, offsetof(struct kvm_vcpu, arch.host_cpu_context));
123 DEFINE(VCPU_TIMER_CNTV_CTL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));
124 DEFINE(VCPU_TIMER_CNTV_CVAL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval));
125 DEFINE(KVM_TIMER_CNTVOFF, offsetof(struct kvm, arch.timer.cntvoff));
126 DEFINE(KVM_TIMER_ENABLED, offsetof(struct kvm, arch.timer.enabled));
127 DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
128 DEFINE(VCPU_VGIC_CPU, offsetof(struct kvm_vcpu, arch.vgic_cpu));
129 DEFINE(VGIC_CPU_HCR, offsetof(struct vgic_cpu, vgic_hcr));
130 DEFINE(VGIC_CPU_VMCR, offsetof(struct vgic_cpu, vgic_vmcr));
131 DEFINE(VGIC_CPU_MISR, offsetof(struct vgic_cpu, vgic_misr));
132 DEFINE(VGIC_CPU_EISR, offsetof(struct vgic_cpu, vgic_eisr));
133 DEFINE(VGIC_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_elrsr));
134 DEFINE(VGIC_CPU_APR, offsetof(struct vgic_cpu, vgic_apr));
135 DEFINE(VGIC_CPU_LR, offsetof(struct vgic_cpu, vgic_lr));
136 DEFINE(VGIC_CPU_NR_LR, offsetof(struct vgic_cpu, nr_lr));
137 DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr));
138 DEFINE(KVM_VGIC_VCTRL, offsetof(struct kvm, arch.vgic.vctrl_base));
139#endif
Catalin Marinas0be73202012-03-05 11:49:26 +0000[diff] [blame]140 return 0;
141}