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Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Andrew Lunn6d917822017-05-26 01:03:21 +02002/*
3 * Marvell 88E6xxx SERDES manipulation, via SMI bus
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
Andrew Lunn6d917822017-05-26 01:03:21 +02008 */
9
10#ifndef _MV88E6XXX_SERDES_H
11#define _MV88E6XXX_SERDES_H
12
Vivien Didelot4d5f2ba72017-06-02 17:06:15 -040013#include "chip.h"
Andrew Lunn6d917822017-05-26 01:03:21 +020014
15#define MV88E6352_ADDR_SERDES 0x0f
16#define MV88E6352_SERDES_PAGE_FIBER 0x01
Andrew Lunn43821722018-09-02 18:13:15 +020017#define MV88E6352_SERDES_IRQ 0x0b
18#define MV88E6352_SERDES_INT_ENABLE 0x12
19#define MV88E6352_SERDES_INT_SPEED_CHANGE BIT(14)
20#define MV88E6352_SERDES_INT_DUPLEX_CHANGE BIT(13)
21#define MV88E6352_SERDES_INT_PAGE_RX BIT(12)
22#define MV88E6352_SERDES_INT_AN_COMPLETE BIT(11)
23#define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10)
24#define MV88E6352_SERDES_INT_SYMBOL_ERROR BIT(9)
25#define MV88E6352_SERDES_INT_FALSE_CARRIER BIT(8)
26#define MV88E6352_SERDES_INT_FIFO_OVER_UNDER BIT(7)
27#define MV88E6352_SERDES_INT_FIBRE_ENERGY BIT(4)
28#define MV88E6352_SERDES_INT_STATUS 0x13
29
Andrew Lunn6d917822017-05-26 01:03:21 +020030
Marek BehĂșnd3cf7d82019-08-26 23:31:53 +020031#define MV88E6341_PORT5_LANE 0x15
Marek BehĂșn5bafeb6e2018-05-04 19:26:10 +020032
Andrew Lunn6335e9f2017-05-26 01:03:23 +020033#define MV88E6390_PORT9_LANE0 0x09
34#define MV88E6390_PORT9_LANE1 0x12
35#define MV88E6390_PORT9_LANE2 0x13
36#define MV88E6390_PORT9_LANE3 0x14
37#define MV88E6390_PORT10_LANE0 0x0a
38#define MV88E6390_PORT10_LANE1 0x15
39#define MV88E6390_PORT10_LANE2 0x16
40#define MV88E6390_PORT10_LANE3 0x17
Andrew Lunn6335e9f2017-05-26 01:03:23 +020041
42/* 10GBASE-R and 10GBASE-X4/X2 */
43#define MV88E6390_PCS_CONTROL_1 0x1000
44#define MV88E6390_PCS_CONTROL_1_RESET BIT(15)
45#define MV88E6390_PCS_CONTROL_1_LOOPBACK BIT(14)
46#define MV88E6390_PCS_CONTROL_1_SPEED BIT(13)
47#define MV88E6390_PCS_CONTROL_1_PDOWN BIT(11)
48
49/* 1000BASE-X and SGMII */
50#define MV88E6390_SGMII_CONTROL 0x2000
51#define MV88E6390_SGMII_CONTROL_RESET BIT(15)
52#define MV88E6390_SGMII_CONTROL_LOOPBACK BIT(14)
53#define MV88E6390_SGMII_CONTROL_PDOWN BIT(11)
Andrew Lunnefd1ba62018-08-09 15:38:48 +020054#define MV88E6390_SGMII_STATUS 0x2001
55#define MV88E6390_SGMII_STATUS_AN_DONE BIT(5)
56#define MV88E6390_SGMII_STATUS_REMOTE_FAULT BIT(4)
57#define MV88E6390_SGMII_STATUS_LINK BIT(2)
58#define MV88E6390_SGMII_INT_ENABLE 0xa001
59#define MV88E6390_SGMII_INT_SPEED_CHANGE BIT(14)
60#define MV88E6390_SGMII_INT_DUPLEX_CHANGE BIT(13)
61#define MV88E6390_SGMII_INT_PAGE_RX BIT(12)
62#define MV88E6390_SGMII_INT_AN_COMPLETE BIT(11)
63#define MV88E6390_SGMII_INT_LINK_DOWN BIT(10)
64#define MV88E6390_SGMII_INT_LINK_UP BIT(9)
65#define MV88E6390_SGMII_INT_SYMBOL_ERROR BIT(8)
66#define MV88E6390_SGMII_INT_FALSE_CARRIER BIT(7)
67#define MV88E6390_SGMII_INT_STATUS 0xa002
Heiner Kallweit72d8b4f2019-03-01 20:41:00 +010068#define MV88E6390_SGMII_PHY_STATUS 0xa003
69#define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK GENMASK(15, 14)
70#define MV88E6390_SGMII_PHY_STATUS_SPEED_1000 0x8000
71#define MV88E6390_SGMII_PHY_STATUS_SPEED_100 0x4000
72#define MV88E6390_SGMII_PHY_STATUS_SPEED_10 0x0000
73#define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL BIT(13)
74#define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11)
75#define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10)
Andrew Lunn6335e9f2017-05-26 01:03:23 +020076
Nikita Yushchenko0df95282019-12-25 08:22:38 +030077/* Packet generator pad packet checker */
78#define MV88E6390_PG_CONTROL 0xf010
79#define MV88E6390_PG_CONTROL_ENABLE_PC BIT(0)
80
Vivien Didelot5122d4e2019-08-31 16:18:30 -040081u8 mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
Vivien Didelot9db4a722019-08-31 16:18:31 -040082u8 mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
Vivien Didelot5122d4e2019-08-31 16:18:30 -040083u8 mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
84u8 mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
Vivien Didelot4241ef52019-08-31 16:18:29 -040085unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
86 int port);
87unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
88 int port);
Vivien Didelotdc272f62019-08-31 16:18:33 -040089int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
90 bool on);
91int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
92 bool on);
Vivien Didelot61a46b42019-08-31 16:18:34 -040093int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane,
94 bool enable);
95int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane,
96 bool enable);
Vivien Didelot907b9b92019-08-31 16:18:35 -040097irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
98 u8 lane);
99irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
100 u8 lane);
Andrew Lunncda9f4a2018-03-01 02:02:31 +0100101int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
Andrew Lunn65f60e42018-03-28 23:50:28 +0200102int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
103 int port, uint8_t *data);
104int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
105 uint64_t *data);
Nikita Yushchenko0df95282019-12-25 08:22:38 +0300106int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
107int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
108 int port, uint8_t *data);
109int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
110 uint64_t *data);
Andrew Lunn43821722018-09-02 18:13:15 +0200111
Andrew Lunnd3f88a22020-02-16 18:54:14 +0100112int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
113void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
114
Vivien Didelot5122d4e2019-08-31 16:18:30 -0400115/* Return the (first) SERDES lane address a port is using, 0 otherwise. */
116static inline u8 mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
117 int port)
118{
119 if (!chip->info->ops->serdes_get_lane)
120 return 0;
121
122 return chip->info->ops->serdes_get_lane(chip, port);
123}
124
Vivien Didelotdc272f62019-08-31 16:18:33 -0400125static inline int mv88e6xxx_serdes_power_up(struct mv88e6xxx_chip *chip,
126 int port, u8 lane)
127{
128 if (!chip->info->ops->serdes_power)
129 return -EOPNOTSUPP;
130
131 return chip->info->ops->serdes_power(chip, port, lane, true);
132}
133
134static inline int mv88e6xxx_serdes_power_down(struct mv88e6xxx_chip *chip,
135 int port, u8 lane)
136{
137 if (!chip->info->ops->serdes_power)
138 return -EOPNOTSUPP;
139
140 return chip->info->ops->serdes_power(chip, port, lane, false);
141}
142
Vivien Didelot4241ef52019-08-31 16:18:29 -0400143static inline unsigned int
144mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
145{
146 if (!chip->info->ops->serdes_irq_mapping)
147 return 0;
148
149 return chip->info->ops->serdes_irq_mapping(chip, port);
150}
Andrew Lunn734447d2018-08-09 15:38:49 +0200151
Vivien Didelot61a46b42019-08-31 16:18:34 -0400152static inline int mv88e6xxx_serdes_irq_enable(struct mv88e6xxx_chip *chip,
153 int port, u8 lane)
154{
155 if (!chip->info->ops->serdes_irq_enable)
156 return -EOPNOTSUPP;
157
158 return chip->info->ops->serdes_irq_enable(chip, port, lane, true);
159}
160
161static inline int mv88e6xxx_serdes_irq_disable(struct mv88e6xxx_chip *chip,
162 int port, u8 lane)
163{
164 if (!chip->info->ops->serdes_irq_enable)
165 return -EOPNOTSUPP;
166
167 return chip->info->ops->serdes_irq_enable(chip, port, lane, false);
168}
169
Vivien Didelot907b9b92019-08-31 16:18:35 -0400170static inline irqreturn_t
171mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, u8 lane)
172{
173 if (!chip->info->ops->serdes_irq_status)
174 return IRQ_NONE;
175
176 return chip->info->ops->serdes_irq_status(chip, port, lane);
177}
178
Andrew Lunn6d917822017-05-26 01:03:21 +0200179#endif