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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 4fa04299184604d5ae85a3ebe795e19eb564fc67 / . / arch / arm64 / boot / dts / renesas / r8a7795.dtsi
blob: 348baebffeac0e3ba544ed44aaec65f7dbd638ac [file] [log] [blame]
Simon Horman26a7e062015-11-17 02:42:32 +0900[diff] [blame]1/*
2 * Device Tree Source for the r8a7795 SoC
3 *
4 * Copyright (C) 2015 Renesas Electronics Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Geert Uytterhoeven49af46b2015-10-02 11:55:51 +0900[diff] [blame]11#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
Simon Horman26a7e062015-11-17 02:42:32 +0900[diff] [blame]12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14/ {
15 compatible = "renesas,r8a7795";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
Kuninori Morimoto32bc0c52015-10-28 08:05:27 +0900[diff] [blame]19 aliases {
20 i2c0 = &i2c0;
21 i2c1 = &i2c1;
22 i2c2 = &i2c2;
23 i2c3 = &i2c3;
24 i2c4 = &i2c4;
25 i2c5 = &i2c5;
26 i2c6 = &i2c6;
27 };
28
Simon Horman26a7e062015-11-17 02:42:32 +0900[diff] [blame]29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 /* 1 core only at this point */
34 a57_0: cpu@0 {
35 compatible = "arm,cortex-a57", "arm,armv8";
36 reg = <0x0>;
37 device_type = "cpu";
38 };
39 };
40
41 extal_clk: extal {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 /* This value must be overridden by the board */
45 clock-frequency = <0>;
46 };
47
48 extalr_clk: extalr {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 /* This value must be overridden by the board */
52 clock-frequency = <0>;
53 };
54
55 soc {
56 compatible = "simple-bus";
57 interrupt-parent = <&gic>;
58 #address-cells = <2>;
59 #size-cells = <2>;
60 ranges;
61
62 gic: interrupt-controller@0xf1010000 {
63 compatible = "arm,gic-400";
64 #interrupt-cells = <3>;
65 #address-cells = <0>;
66 interrupt-controller;
67 reg = <0x0 0xf1010000 0 0x1000>,
68 <0x0 0xf1020000 0 0x2000>;
69 interrupts = <GIC_PPI 9
70 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
71 };
72
Takeshi Kihara7b086232015-10-29 08:09:18 +0900[diff] [blame]73 gpio0: gpio@e6050000 {
74 compatible = "renesas,gpio-r8a7795",
75 "renesas,gpio-rcar";
76 reg = <0 0xe6050000 0 0x50>;
77 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
78 #gpio-cells = <2>;
79 gpio-controller;
80 gpio-ranges = <&pfc 0 0 16>;
81 #interrupt-cells = <2>;
82 interrupt-controller;
83 clocks = <&cpg CPG_MOD 912>;
84 power-domains = <&cpg>;
85 };
86
87 gpio1: gpio@e6051000 {
88 compatible = "renesas,gpio-r8a7795",
89 "renesas,gpio-rcar";
90 reg = <0 0xe6051000 0 0x50>;
91 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
92 #gpio-cells = <2>;
93 gpio-controller;
94 gpio-ranges = <&pfc 0 32 28>;
95 #interrupt-cells = <2>;
96 interrupt-controller;
97 clocks = <&cpg CPG_MOD 911>;
98 power-domains = <&cpg>;
99 };
100
101 gpio2: gpio@e6052000 {
102 compatible = "renesas,gpio-r8a7795",
103 "renesas,gpio-rcar";
104 reg = <0 0xe6052000 0 0x50>;
105 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
106 #gpio-cells = <2>;
107 gpio-controller;
108 gpio-ranges = <&pfc 0 64 15>;
109 #interrupt-cells = <2>;
110 interrupt-controller;
111 clocks = <&cpg CPG_MOD 910>;
112 power-domains = <&cpg>;
113 };
114
115 gpio3: gpio@e6053000 {
116 compatible = "renesas,gpio-r8a7795",
117 "renesas,gpio-rcar";
118 reg = <0 0xe6053000 0 0x50>;
119 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
120 #gpio-cells = <2>;
121 gpio-controller;
122 gpio-ranges = <&pfc 0 96 16>;
123 #interrupt-cells = <2>;
124 interrupt-controller;
125 clocks = <&cpg CPG_MOD 909>;
126 power-domains = <&cpg>;
127 };
128
129 gpio4: gpio@e6054000 {
130 compatible = "renesas,gpio-r8a7795",
131 "renesas,gpio-rcar";
132 reg = <0 0xe6054000 0 0x50>;
133 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
134 #gpio-cells = <2>;
135 gpio-controller;
136 gpio-ranges = <&pfc 0 128 18>;
137 #interrupt-cells = <2>;
138 interrupt-controller;
139 clocks = <&cpg CPG_MOD 908>;
140 power-domains = <&cpg>;
141 };
142
143 gpio5: gpio@e6055000 {
144 compatible = "renesas,gpio-r8a7795",
145 "renesas,gpio-rcar";
146 reg = <0 0xe6055000 0 0x50>;
147 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
148 #gpio-cells = <2>;
149 gpio-controller;
150 gpio-ranges = <&pfc 0 160 26>;
151 #interrupt-cells = <2>;
152 interrupt-controller;
153 clocks = <&cpg CPG_MOD 907>;
154 power-domains = <&cpg>;
155 };
156
157 gpio6: gpio@e6055400 {
158 compatible = "renesas,gpio-r8a7795",
159 "renesas,gpio-rcar";
160 reg = <0 0xe6055400 0 0x50>;
161 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
162 #gpio-cells = <2>;
163 gpio-controller;
164 gpio-ranges = <&pfc 0 192 32>;
165 #interrupt-cells = <2>;
166 interrupt-controller;
167 clocks = <&cpg CPG_MOD 906>;
168 power-domains = <&cpg>;
169 };
170
171 gpio7: gpio@e6055800 {
172 compatible = "renesas,gpio-r8a7795",
173 "renesas,gpio-rcar";
174 reg = <0 0xe6055800 0 0x50>;
175 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
176 #gpio-cells = <2>;
177 gpio-controller;
178 gpio-ranges = <&pfc 0 224 4>;
179 #interrupt-cells = <2>;
180 interrupt-controller;
181 clocks = <&cpg CPG_MOD 905>;
182 power-domains = <&cpg>;
183 };
184
Simon Horman26a7e062015-11-17 02:42:32 +0900[diff] [blame]185 timer {
186 compatible = "arm,armv8-timer";
187 interrupts = <GIC_PPI 13
188 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
189 <GIC_PPI 14
190 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
191 <GIC_PPI 11
192 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
193 <GIC_PPI 10
194 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
195 };
196
197 cpg: clock-controller@e6150000 {
198 compatible = "renesas,r8a7795-cpg-mssr";
199 reg = <0 0xe6150000 0 0x1000>;
200 clocks = <&extal_clk>, <&extalr_clk>;
201 clock-names = "extal", "extalr";
202 #clock-cells = <2>;
203 #power-domain-cells = <0>;
204 };
Geert Uytterhoevend9202122015-10-02 11:55:40 +0900[diff] [blame]205
Kuninori Morimoto92418442015-10-02 11:56:01 +0900[diff] [blame]206 pfc: pfc@e6060000 {
207 compatible = "renesas,pfc-r8a7795";
208 reg = <0 0xe6060000 0 0x50c>;
209 };
210
Geert Uytterhoevend9202122015-10-02 11:55:40 +0900[diff] [blame]211 dmac0: dma-controller@e6700000 {
212 /* Empty node for now */
213 };
214
215 dmac1: dma-controller@e7300000 {
216 /* Empty node for now */
217 };
218
219 dmac2: dma-controller@e7310000 {
220 /* Empty node for now */
221 };
Geert Uytterhoeven49af46b2015-10-02 11:55:51 +0900[diff] [blame]222
Kazuya Mizuguchia92843c2015-11-02 13:31:44 +0900[diff] [blame]223 avb: ethernet@e6800000 {
224 compatible = "renesas,etheravb-r8a7795";
225 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
226 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
251 interrupt-names = "ch0", "ch1", "ch2", "ch3",
252 "ch4", "ch5", "ch6", "ch7",
253 "ch8", "ch9", "ch10", "ch11",
254 "ch12", "ch13", "ch14", "ch15",
255 "ch16", "ch17", "ch18", "ch19",
256 "ch20", "ch21", "ch22", "ch23",
257 "ch24";
258 clocks = <&cpg CPG_MOD 812>;
259 power-domains = <&cpg>;
260 phy-mode = "rgmii-id";
261 #address-cells = <1>;
262 #size-cells = <0>;
263 };
264
Geert Uytterhoeven4fa04292015-11-19 19:29:11 +0100[diff] [blame^]265 hscif0: serial@e6540000 {
266 compatible = "renesas,hscif-r8a7795", "renesas,hscif";
267 reg = <0 0xe6540000 0 96>;
268 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&cpg CPG_MOD 520>;
270 clock-names = "sci_ick";
271 dmas = <&dmac1 0x31>, <&dmac1 0x30>;
272 dma-names = "tx", "rx";
273 power-domains = <&cpg>;
274 status = "disabled";
275 };
276
277 hscif1: serial@e6550000 {
278 compatible = "renesas,hscif-r8a7795", "renesas,hscif";
279 reg = <0 0xe6550000 0 96>;
280 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&cpg CPG_MOD 519>;
282 clock-names = "sci_ick";
283 dmas = <&dmac1 0x33>, <&dmac1 0x32>;
284 dma-names = "tx", "rx";
285 power-domains = <&cpg>;
286 status = "disabled";
287 };
288
289 hscif2: serial@e6560000 {
290 compatible = "renesas,hscif-r8a7795", "renesas,hscif";
291 reg = <0 0xe6560000 0 96>;
292 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&cpg CPG_MOD 518>;
294 clock-names = "sci_ick";
295 dmas = <&dmac1 0x35>, <&dmac1 0x34>;
296 dma-names = "tx", "rx";
297 power-domains = <&cpg>;
298 status = "disabled";
299 };
300
301 hscif3: serial@e66a0000 {
302 compatible = "renesas,hscif-r8a7795", "renesas,hscif";
303 reg = <0 0xe66a0000 0 96>;
304 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cpg CPG_MOD 517>;
306 clock-names = "sci_ick";
307 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
308 dma-names = "tx", "rx";
309 power-domains = <&cpg>;
310 status = "disabled";
311 };
312
313 hscif4: serial@e66b0000 {
314 compatible = "renesas,hscif-r8a7795", "renesas,hscif";
315 reg = <0 0xe66b0000 0 96>;
316 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&cpg CPG_MOD 516>;
318 clock-names = "sci_ick";
319 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
320 dma-names = "tx", "rx";
321 power-domains = <&cpg>;
322 status = "disabled";
323 };
324
Geert Uytterhoeven49af46b2015-10-02 11:55:51 +0900[diff] [blame]325 scif0: serial@e6e60000 {
326 compatible = "renesas,scif-r8a7795", "renesas,scif";
327 reg = <0 0xe6e60000 0 64>;
328 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&cpg CPG_MOD 207>;
330 clock-names = "sci_ick";
331 dmas = <&dmac1 0x51>, <&dmac1 0x50>;
332 dma-names = "tx", "rx";
333 power-domains = <&cpg>;
334 status = "disabled";
335 };
336
337 scif1: serial@e6e68000 {
338 compatible = "renesas,scif-r8a7795", "renesas,scif";
339 reg = <0 0xe6e68000 0 64>;
340 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&cpg CPG_MOD 206>;
342 clock-names = "sci_ick";
343 dmas = <&dmac1 0x53>, <&dmac1 0x52>;
344 dma-names = "tx", "rx";
345 power-domains = <&cpg>;
346 status = "disabled";
347 };
348
349 scif2: serial@e6e88000 {
350 compatible = "renesas,scif-r8a7795", "renesas,scif";
351 reg = <0 0xe6e88000 0 64>;
352 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&cpg CPG_MOD 310>;
354 clock-names = "sci_ick";
355 dmas = <&dmac1 0x13>, <&dmac1 0x12>;
356 dma-names = "tx", "rx";
357 power-domains = <&cpg>;
358 status = "disabled";
359 };
360
361 scif3: serial@e6c50000 {
362 compatible = "renesas,scif-r8a7795", "renesas,scif";
363 reg = <0 0xe6c50000 0 64>;
364 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&cpg CPG_MOD 204>;
366 clock-names = "sci_ick";
367 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
368 dma-names = "tx", "rx";
369 power-domains = <&cpg>;
370 status = "disabled";
371 };
372
373 scif4: serial@e6c40000 {
374 compatible = "renesas,scif-r8a7795", "renesas,scif";
375 reg = <0 0xe6c40000 0 64>;
376 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&cpg CPG_MOD 203>;
378 clock-names = "sci_ick";
379 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
380 dma-names = "tx", "rx";
381 power-domains = <&cpg>;
382 status = "disabled";
383 };
384
385 scif5: serial@e6f30000 {
386 compatible = "renesas,scif-r8a7795", "renesas,scif";
387 reg = <0 0xe6f30000 0 64>;
388 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&cpg CPG_MOD 202>;
390 clock-names = "sci_ick";
391 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
392 dma-names = "tx", "rx";
393 power-domains = <&cpg>;
394 status = "disabled";
395 };
Kuninori Morimoto32bc0c52015-10-28 08:05:27 +0900[diff] [blame]396
397 i2c0: i2c@e6500000 {
398 #address-cells = <1>;
399 #size-cells = <0>;
400 compatible = "renesas,i2c-r8a7795";
401 reg = <0 0xe6500000 0 0x40>;
402 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&cpg CPG_MOD 931>;
404 power-domains = <&cpg>;
405 status = "disabled";
406 };
407
408 i2c1: i2c@e6508000 {
409 #address-cells = <1>;
410 #size-cells = <0>;
411 compatible = "renesas,i2c-r8a7795";
412 reg = <0 0xe6508000 0 0x40>;
413 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cpg CPG_MOD 930>;
415 power-domains = <&cpg>;
416 status = "disabled";
417 };
418
419 i2c2: i2c@e6510000 {
420 #address-cells = <1>;
421 #size-cells = <0>;
422 compatible = "renesas,i2c-r8a7795";
423 reg = <0 0xe6510000 0 0x40>;
424 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&cpg CPG_MOD 929>;
426 power-domains = <&cpg>;
427 status = "disabled";
428 };
429
430 i2c3: i2c@e66d0000 {
431 #address-cells = <1>;
432 #size-cells = <0>;
433 compatible = "renesas,i2c-r8a7795";
434 reg = <0 0xe66d0000 0 0x40>;
435 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&cpg CPG_MOD 928>;
437 power-domains = <&cpg>;
438 status = "disabled";
439 };
440
441 i2c4: i2c@e66d8000 {
442 #address-cells = <1>;
443 #size-cells = <0>;
444 compatible = "renesas,i2c-r8a7795";
445 reg = <0 0xe66d8000 0 0x40>;
446 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&cpg CPG_MOD 927>;
448 power-domains = <&cpg>;
449 status = "disabled";
450 };
451
452 i2c5: i2c@e66e0000 {
453 #address-cells = <1>;
454 #size-cells = <0>;
455 compatible = "renesas,i2c-r8a7795";
456 reg = <0 0xe66e0000 0 0x40>;
457 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&cpg CPG_MOD 919>;
459 power-domains = <&cpg>;
460 status = "disabled";
461 };
462
463 i2c6: i2c@e66e8000 {
464 #address-cells = <1>;
465 #size-cells = <0>;
466 compatible = "renesas,i2c-r8a7795";
467 reg = <0 0xe66e8000 0 0x40>;
468 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cpg CPG_MOD 918>;
470 power-domains = <&cpg>;
471 status = "disabled";
472 };
Simon Horman26a7e062015-11-17 02:42:32 +0900[diff] [blame]473 };
474};