blob: 11680c532b383f302e4229446856fdb018935510 [file] [log] [blame]
Erik Gillingc5f80062010-01-21 16:53:02 -08001if ARCH_TEGRA
2
3comment "NVIDIA Tegra options"
4
Erik Gillingc5f80062010-01-21 16:53:02 -08005config ARCH_TEGRA_2x_SOC
Peter De Schrijver44107d82011-12-14 17:03:25 +02006 bool "Enable support for Tegra20 family"
Erik Gillingc5f80062010-01-21 16:53:02 -08007 select CPU_V7
8 select ARM_GIC
Erik Gilling3c92db92010-03-15 19:40:06 -07009 select ARCH_REQUIRE_GPIOLIB
Stephen Warrenf1f1ffa2012-02-01 14:04:48 -070010 select PINCTRL
11 select PINCTRL_TEGRA20
Benoit Goby91525d02011-03-09 16:28:55 -080012 select USB_ARCH_HAS_EHCI if USB_SUPPORT
Arnd Bergmann279b6582012-03-02 17:26:00 -050013 select USB_ULPI if USB
Benoit Goby91525d02011-03-09 16:28:55 -080014 select USB_ULPI_VIEWPORT if USB_SUPPORT
Stephen Warrenf35b4312012-02-14 13:39:39 -070015 select ARM_ERRATA_720789
16 select ARM_ERRATA_742230
17 select ARM_ERRATA_751472
18 select ARM_ERRATA_754327
Arnd Bergmann8f90cce2012-08-16 09:36:04 +000019 select ARM_ERRATA_764369 if SMP
Stephen Warrenf35b4312012-02-14 13:39:39 -070020 select PL310_ERRATA_727915 if CACHE_L2X0
21 select PL310_ERRATA_769419 if CACHE_L2X0
Arnd Bergmann013df382012-03-02 15:58:28 -050022 select CPU_FREQ_TABLE if CPU_FREQ
Erik Gillingc5f80062010-01-21 16:53:02 -080023 help
24 Support for NVIDIA Tegra AP20 and T20 processors, based on the
25 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
26
Peter De Schrijver44107d82011-12-14 17:03:25 +020027config ARCH_TEGRA_3x_SOC
28 bool "Enable support for Tegra30 family"
29 select CPU_V7
30 select ARM_GIC
31 select ARCH_REQUIRE_GPIOLIB
Stephen Warrenf1f1ffa2012-02-01 14:04:48 -070032 select PINCTRL
33 select PINCTRL_TEGRA30
Peter De Schrijver44107d82011-12-14 17:03:25 +020034 select USB_ARCH_HAS_EHCI if USB_SUPPORT
Arnd Bergmann279b6582012-03-02 17:26:00 -050035 select USB_ULPI if USB
Peter De Schrijver44107d82011-12-14 17:03:25 +020036 select USB_ULPI_VIEWPORT if USB_SUPPORT
Stephen Warrenf35b4312012-02-14 13:39:39 -070037 select ARM_ERRATA_743622
38 select ARM_ERRATA_751472
39 select ARM_ERRATA_754322
Arnd Bergmann8f90cce2012-08-16 09:36:04 +000040 select ARM_ERRATA_764369 if SMP
Stephen Warrenf35b4312012-02-14 13:39:39 -070041 select PL310_ERRATA_769419 if CACHE_L2X0
Arnd Bergmann013df382012-03-02 15:58:28 -050042 select CPU_FREQ_TABLE if CPU_FREQ
Peter De Schrijver44107d82011-12-14 17:03:25 +020043 help
44 Support for NVIDIA Tegra T30 processor family, based on the
45 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
Erik Gillingc5f80062010-01-21 16:53:02 -080046
Mike Rapoport77ffc142010-09-27 11:26:33 +020047config TEGRA_PCI
48 bool "PCI Express support"
Peter De Schrijverb2bbbc42011-12-14 17:03:14 +020049 depends on ARCH_TEGRA_2x_SOC
Mike Rapoport77ffc142010-09-27 11:26:33 +020050 select PCI
51
Hiroshi DOYU87d0bab22012-05-07 12:24:48 +020052config TEGRA_AHB
53 bool "Enable AHB driver for NVIDIA Tegra SoCs"
54 default y
55 help
56 Adds AHB configuration functionality for NVIDIA Tegra SoCs,
57 which controls AHB bus master arbitration and some
58 perfomance parameters(priority, prefech size).
59
Erik Gillingc5f80062010-01-21 16:53:02 -080060choice
Stephen Warren80881da2012-03-26 12:49:57 -060061 prompt "Default low-level debug console UART"
Erik Gillingc5f80062010-01-21 16:53:02 -080062 default TEGRA_DEBUG_UART_NONE
63
64config TEGRA_DEBUG_UART_NONE
65 bool "None"
66
67config TEGRA_DEBUG_UARTA
68 bool "UART-A"
69
70config TEGRA_DEBUG_UARTB
71 bool "UART-B"
72
73config TEGRA_DEBUG_UARTC
74 bool "UART-C"
75
76config TEGRA_DEBUG_UARTD
77 bool "UART-D"
78
79config TEGRA_DEBUG_UARTE
80 bool "UART-E"
81
82endchoice
83
Stephen Warren80881da2012-03-26 12:49:57 -060084choice
85 prompt "Automatic low-level debug console UART"
86 default TEGRA_DEBUG_UART_AUTO_NONE
87
88config TEGRA_DEBUG_UART_AUTO_NONE
89 bool "None"
90
91config TEGRA_DEBUG_UART_AUTO_ODMDATA
92 bool "Via ODMDATA"
93 help
94 Automatically determines which UART to use for low-level debug based
95 on the ODMDATA value. This value is part of the BCT, and is written
96 to the boot memory device using nvflash, or other flashing tool.
97 When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
98 0/1/2/3/4 are UART A/B/C/D/E.
99
100config TEGRA_DEBUG_UART_AUTO_SCRATCH
101 bool "Via UART scratch register"
102 help
103 Automatically determines which UART to use for low-level debug based
104 on the UART scratch register value. Some bootloaders put ASCII 'D'
105 in this register when they initialize their own console UART output.
106 Using this option allows the kernel to automatically pick the same
107 UART.
108
109endchoice
110
Colin Crossefdf72a2011-02-12 18:22:49 -0800111config TEGRA_EMC_SCALING_ENABLE
112 bool "Enable scaling the memory frequency"
Mark Brown38376862011-02-22 20:35:24 +0000113
114endif