blob: 5fad787ba012b3fe85485b463162f3deb4286c95 [file] [log] [blame]
Suman Annad4ce2de2020-12-08 15:09:58 +01001// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * PRU-ICSS remoteproc driver for various TI SoCs
4 *
5 * Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/
6 *
7 * Author(s):
8 * Suman Anna <s-anna@ti.com>
9 * Andrew F. Davis <afd@ti.com>
10 * Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> for Texas Instruments
11 */
12
13#include <linux/bitops.h>
Suman Anna20ad1de2020-12-08 15:10:00 +010014#include <linux/debugfs.h>
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +010015#include <linux/irqdomain.h>
Suman Annad4ce2de2020-12-08 15:09:58 +010016#include <linux/module.h>
17#include <linux/of_device.h>
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +010018#include <linux/of_irq.h>
Suman Annad4ce2de2020-12-08 15:09:58 +010019#include <linux/pruss_driver.h>
20#include <linux/remoteproc.h>
21
22#include "remoteproc_internal.h"
23#include "remoteproc_elf_helpers.h"
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +010024#include "pru_rproc.h"
Suman Annad4ce2de2020-12-08 15:09:58 +010025
26/* PRU_ICSS_PRU_CTRL registers */
27#define PRU_CTRL_CTRL 0x0000
28#define PRU_CTRL_STS 0x0004
Suman Anna20ad1de2020-12-08 15:10:00 +010029#define PRU_CTRL_WAKEUP_EN 0x0008
30#define PRU_CTRL_CYCLE 0x000C
31#define PRU_CTRL_STALL 0x0010
32#define PRU_CTRL_CTBIR0 0x0020
33#define PRU_CTRL_CTBIR1 0x0024
34#define PRU_CTRL_CTPPR0 0x0028
35#define PRU_CTRL_CTPPR1 0x002C
Suman Annad4ce2de2020-12-08 15:09:58 +010036
37/* CTRL register bit-fields */
38#define CTRL_CTRL_SOFT_RST_N BIT(0)
39#define CTRL_CTRL_EN BIT(1)
40#define CTRL_CTRL_SLEEPING BIT(2)
41#define CTRL_CTRL_CTR_EN BIT(3)
42#define CTRL_CTRL_SINGLE_STEP BIT(8)
43#define CTRL_CTRL_RUNSTATE BIT(15)
44
Suman Anna20ad1de2020-12-08 15:10:00 +010045/* PRU_ICSS_PRU_DEBUG registers */
46#define PRU_DEBUG_GPREG(x) (0x0000 + (x) * 4)
47#define PRU_DEBUG_CT_REG(x) (0x0080 + (x) * 4)
48
Suman Anna1d39f4d2020-12-08 15:10:01 +010049/* PRU/RTU/Tx_PRU Core IRAM address masks */
Suman Annad4ce2de2020-12-08 15:09:58 +010050#define PRU_IRAM_ADDR_MASK 0x3ffff
51#define PRU0_IRAM_ADDR_MASK 0x34000
52#define PRU1_IRAM_ADDR_MASK 0x38000
Suman Anna1d39f4d2020-12-08 15:10:01 +010053#define RTU0_IRAM_ADDR_MASK 0x4000
54#define RTU1_IRAM_ADDR_MASK 0x6000
55#define TX_PRU0_IRAM_ADDR_MASK 0xa000
56#define TX_PRU1_IRAM_ADDR_MASK 0xc000
Suman Annad4ce2de2020-12-08 15:09:58 +010057
58/* PRU device addresses for various type of PRU RAMs */
59#define PRU_IRAM_DA 0 /* Instruction RAM */
60#define PRU_PDRAM_DA 0 /* Primary Data RAM */
61#define PRU_SDRAM_DA 0x2000 /* Secondary Data RAM */
62#define PRU_SHRDRAM_DA 0x10000 /* Shared Data RAM */
63
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +010064#define MAX_PRU_SYS_EVENTS 160
65
Suman Annad4ce2de2020-12-08 15:09:58 +010066/**
67 * enum pru_iomem - PRU core memory/register range identifiers
68 *
69 * @PRU_IOMEM_IRAM: PRU Instruction RAM range
70 * @PRU_IOMEM_CTRL: PRU Control register range
71 * @PRU_IOMEM_DEBUG: PRU Debug register range
72 * @PRU_IOMEM_MAX: just keep this one at the end
73 */
74enum pru_iomem {
75 PRU_IOMEM_IRAM = 0,
76 PRU_IOMEM_CTRL,
77 PRU_IOMEM_DEBUG,
78 PRU_IOMEM_MAX,
79};
80
81/**
Suman Anna1d39f4d2020-12-08 15:10:01 +010082 * enum pru_type - PRU core type identifier
83 *
84 * @PRU_TYPE_PRU: Programmable Real-time Unit
85 * @PRU_TYPE_RTU: Auxiliary Programmable Real-Time Unit
86 * @PRU_TYPE_TX_PRU: Transmit Programmable Real-Time Unit
87 * @PRU_TYPE_MAX: just keep this one at the end
88 */
89enum pru_type {
90 PRU_TYPE_PRU = 0,
91 PRU_TYPE_RTU,
92 PRU_TYPE_TX_PRU,
93 PRU_TYPE_MAX,
94};
95
96/**
97 * struct pru_private_data - device data for a PRU core
98 * @type: type of the PRU core (PRU, RTU, Tx_PRU)
99 * @is_k3: flag used to identify the need for special load handling
100 */
101struct pru_private_data {
102 enum pru_type type;
103 unsigned int is_k3 : 1;
104};
105
106/**
Suman Annad4ce2de2020-12-08 15:09:58 +0100107 * struct pru_rproc - PRU remoteproc structure
108 * @id: id of the PRU core within the PRUSS
109 * @dev: PRU core device pointer
110 * @pruss: back-reference to parent PRUSS structure
111 * @rproc: remoteproc pointer for this PRU core
Suman Anna1d39f4d2020-12-08 15:10:01 +0100112 * @data: PRU core specific data
Suman Annad4ce2de2020-12-08 15:09:58 +0100113 * @mem_regions: data for each of the PRU memory regions
114 * @fw_name: name of firmware image used during loading
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +0100115 * @mapped_irq: virtual interrupt numbers of created fw specific mapping
116 * @pru_interrupt_map: pointer to interrupt mapping description (firmware)
117 * @pru_interrupt_map_sz: pru_interrupt_map size
Suman Anna20ad1de2020-12-08 15:10:00 +0100118 * @dbg_single_step: debug state variable to set PRU into single step mode
119 * @dbg_continuous: debug state variable to restore PRU execution mode
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +0100120 * @evt_count: number of mapped events
Suman Annad4ce2de2020-12-08 15:09:58 +0100121 */
122struct pru_rproc {
123 int id;
124 struct device *dev;
125 struct pruss *pruss;
126 struct rproc *rproc;
Suman Anna1d39f4d2020-12-08 15:10:01 +0100127 const struct pru_private_data *data;
Suman Annad4ce2de2020-12-08 15:09:58 +0100128 struct pruss_mem_region mem_regions[PRU_IOMEM_MAX];
129 const char *fw_name;
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +0100130 unsigned int *mapped_irq;
131 struct pru_irq_rsc *pru_interrupt_map;
132 size_t pru_interrupt_map_sz;
Suman Anna20ad1de2020-12-08 15:10:00 +0100133 u32 dbg_single_step;
134 u32 dbg_continuous;
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +0100135 u8 evt_count;
Suman Annad4ce2de2020-12-08 15:09:58 +0100136};
137
138static inline u32 pru_control_read_reg(struct pru_rproc *pru, unsigned int reg)
139{
140 return readl_relaxed(pru->mem_regions[PRU_IOMEM_CTRL].va + reg);
141}
142
143static inline
144void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val)
145{
146 writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg);
147}
148
Suman Anna20ad1de2020-12-08 15:10:00 +0100149static inline u32 pru_debug_read_reg(struct pru_rproc *pru, unsigned int reg)
150{
151 return readl_relaxed(pru->mem_regions[PRU_IOMEM_DEBUG].va + reg);
152}
153
154static int regs_show(struct seq_file *s, void *data)
155{
156 struct rproc *rproc = s->private;
157 struct pru_rproc *pru = rproc->priv;
158 int i, nregs = 32;
159 u32 pru_sts;
160 int pru_is_running;
161
162 seq_puts(s, "============== Control Registers ==============\n");
163 seq_printf(s, "CTRL := 0x%08x\n",
164 pru_control_read_reg(pru, PRU_CTRL_CTRL));
165 pru_sts = pru_control_read_reg(pru, PRU_CTRL_STS);
166 seq_printf(s, "STS (PC) := 0x%08x (0x%08x)\n", pru_sts, pru_sts << 2);
167 seq_printf(s, "WAKEUP_EN := 0x%08x\n",
168 pru_control_read_reg(pru, PRU_CTRL_WAKEUP_EN));
169 seq_printf(s, "CYCLE := 0x%08x\n",
170 pru_control_read_reg(pru, PRU_CTRL_CYCLE));
171 seq_printf(s, "STALL := 0x%08x\n",
172 pru_control_read_reg(pru, PRU_CTRL_STALL));
173 seq_printf(s, "CTBIR0 := 0x%08x\n",
174 pru_control_read_reg(pru, PRU_CTRL_CTBIR0));
175 seq_printf(s, "CTBIR1 := 0x%08x\n",
176 pru_control_read_reg(pru, PRU_CTRL_CTBIR1));
177 seq_printf(s, "CTPPR0 := 0x%08x\n",
178 pru_control_read_reg(pru, PRU_CTRL_CTPPR0));
179 seq_printf(s, "CTPPR1 := 0x%08x\n",
180 pru_control_read_reg(pru, PRU_CTRL_CTPPR1));
181
182 seq_puts(s, "=============== Debug Registers ===============\n");
183 pru_is_running = pru_control_read_reg(pru, PRU_CTRL_CTRL) &
184 CTRL_CTRL_RUNSTATE;
185 if (pru_is_running) {
186 seq_puts(s, "PRU is executing, cannot print/access debug registers.\n");
187 return 0;
188 }
189
190 for (i = 0; i < nregs; i++) {
191 seq_printf(s, "GPREG%-2d := 0x%08x\tCT_REG%-2d := 0x%08x\n",
192 i, pru_debug_read_reg(pru, PRU_DEBUG_GPREG(i)),
193 i, pru_debug_read_reg(pru, PRU_DEBUG_CT_REG(i)));
194 }
195
196 return 0;
197}
198DEFINE_SHOW_ATTRIBUTE(regs);
199
200/*
201 * Control PRU single-step mode
202 *
203 * This is a debug helper function used for controlling the single-step
204 * mode of the PRU. The PRU Debug registers are not accessible when the
205 * PRU is in RUNNING state.
206 *
207 * Writing a non-zero value sets the PRU into single-step mode irrespective
208 * of its previous state. The PRU mode is saved only on the first set into
209 * a single-step mode. Writing a zero value will restore the PRU into its
210 * original mode.
211 */
212static int pru_rproc_debug_ss_set(void *data, u64 val)
213{
214 struct rproc *rproc = data;
215 struct pru_rproc *pru = rproc->priv;
216 u32 reg_val;
217
218 val = val ? 1 : 0;
219 if (!val && !pru->dbg_single_step)
220 return 0;
221
222 reg_val = pru_control_read_reg(pru, PRU_CTRL_CTRL);
223
224 if (val && !pru->dbg_single_step)
225 pru->dbg_continuous = reg_val;
226
227 if (val)
228 reg_val |= CTRL_CTRL_SINGLE_STEP | CTRL_CTRL_EN;
229 else
230 reg_val = pru->dbg_continuous;
231
232 pru->dbg_single_step = val;
233 pru_control_write_reg(pru, PRU_CTRL_CTRL, reg_val);
234
235 return 0;
236}
237
238static int pru_rproc_debug_ss_get(void *data, u64 *val)
239{
240 struct rproc *rproc = data;
241 struct pru_rproc *pru = rproc->priv;
242
243 *val = pru->dbg_single_step;
244
245 return 0;
246}
247DEFINE_SIMPLE_ATTRIBUTE(pru_rproc_debug_ss_fops, pru_rproc_debug_ss_get,
248 pru_rproc_debug_ss_set, "%llu\n");
249
250/*
251 * Create PRU-specific debugfs entries
252 *
253 * The entries are created only if the parent remoteproc debugfs directory
254 * exists, and will be cleaned up by the remoteproc core.
255 */
256static void pru_rproc_create_debug_entries(struct rproc *rproc)
257{
258 if (!rproc->dbg_dir)
259 return;
260
261 debugfs_create_file("regs", 0400, rproc->dbg_dir,
262 rproc, &regs_fops);
263 debugfs_create_file("single_step", 0600, rproc->dbg_dir,
264 rproc, &pru_rproc_debug_ss_fops);
265}
266
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +0100267static void pru_dispose_irq_mapping(struct pru_rproc *pru)
268{
269 while (pru->evt_count--) {
270 if (pru->mapped_irq[pru->evt_count] > 0)
271 irq_dispose_mapping(pru->mapped_irq[pru->evt_count]);
272 }
273
274 kfree(pru->mapped_irq);
275}
276
277/*
278 * Parse the custom PRU interrupt map resource and configure the INTC
279 * appropriately.
280 */
281static int pru_handle_intrmap(struct rproc *rproc)
282{
283 struct device *dev = rproc->dev.parent;
284 struct pru_rproc *pru = rproc->priv;
285 struct pru_irq_rsc *rsc = pru->pru_interrupt_map;
286 struct irq_fwspec fwspec;
287 struct device_node *irq_parent;
288 int i, ret = 0;
289
290 /* not having pru_interrupt_map is not an error */
291 if (!rsc)
292 return 0;
293
294 /* currently supporting only type 0 */
295 if (rsc->type != 0) {
296 dev_err(dev, "unsupported rsc type: %d\n", rsc->type);
297 return -EINVAL;
298 }
299
300 if (rsc->num_evts > MAX_PRU_SYS_EVENTS)
301 return -EINVAL;
302
303 if (sizeof(*rsc) + rsc->num_evts * sizeof(struct pruss_int_map) !=
304 pru->pru_interrupt_map_sz)
305 return -EINVAL;
306
307 pru->evt_count = rsc->num_evts;
308 pru->mapped_irq = kcalloc(pru->evt_count, sizeof(unsigned int),
309 GFP_KERNEL);
310 if (!pru->mapped_irq)
311 return -ENOMEM;
312
313 /*
314 * parse and fill in system event to interrupt channel and
315 * channel-to-host mapping
316 */
317 irq_parent = of_irq_find_parent(pru->dev->of_node);
318 if (!irq_parent) {
319 kfree(pru->mapped_irq);
320 return -ENODEV;
321 }
322
323 fwspec.fwnode = of_node_to_fwnode(irq_parent);
324 fwspec.param_count = 3;
325 for (i = 0; i < pru->evt_count; i++) {
326 fwspec.param[0] = rsc->pru_intc_map[i].event;
327 fwspec.param[1] = rsc->pru_intc_map[i].chnl;
328 fwspec.param[2] = rsc->pru_intc_map[i].host;
329
330 dev_dbg(dev, "mapping%d: event %d, chnl %d, host %d\n",
331 i, fwspec.param[0], fwspec.param[1], fwspec.param[2]);
332
333 pru->mapped_irq[i] = irq_create_fwspec_mapping(&fwspec);
334 if (!pru->mapped_irq[i]) {
335 dev_err(dev, "failed to get virq\n");
336 ret = pru->mapped_irq[i];
337 goto map_fail;
338 }
339 }
340
341 return ret;
342
343map_fail:
344 pru_dispose_irq_mapping(pru);
345
346 return ret;
347}
348
Suman Annad4ce2de2020-12-08 15:09:58 +0100349static int pru_rproc_start(struct rproc *rproc)
350{
351 struct device *dev = &rproc->dev;
352 struct pru_rproc *pru = rproc->priv;
Suman Anna1d39f4d2020-12-08 15:10:01 +0100353 const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" };
Suman Annad4ce2de2020-12-08 15:09:58 +0100354 u32 val;
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +0100355 int ret;
Suman Annad4ce2de2020-12-08 15:09:58 +0100356
Suman Anna1d39f4d2020-12-08 15:10:01 +0100357 dev_dbg(dev, "starting %s%d: entry-point = 0x%llx\n",
358 names[pru->data->type], pru->id, (rproc->bootaddr >> 2));
Suman Annad4ce2de2020-12-08 15:09:58 +0100359
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +0100360 ret = pru_handle_intrmap(rproc);
361 /*
362 * reset references to pru interrupt map - they will stop being valid
363 * after rproc_start returns
364 */
365 pru->pru_interrupt_map = NULL;
366 pru->pru_interrupt_map_sz = 0;
367 if (ret)
368 return ret;
369
Suman Annad4ce2de2020-12-08 15:09:58 +0100370 val = CTRL_CTRL_EN | ((rproc->bootaddr >> 2) << 16);
371 pru_control_write_reg(pru, PRU_CTRL_CTRL, val);
372
373 return 0;
374}
375
376static int pru_rproc_stop(struct rproc *rproc)
377{
378 struct device *dev = &rproc->dev;
379 struct pru_rproc *pru = rproc->priv;
Suman Anna1d39f4d2020-12-08 15:10:01 +0100380 const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" };
Suman Annad4ce2de2020-12-08 15:09:58 +0100381 u32 val;
382
Suman Anna1d39f4d2020-12-08 15:10:01 +0100383 dev_dbg(dev, "stopping %s%d\n", names[pru->data->type], pru->id);
Suman Annad4ce2de2020-12-08 15:09:58 +0100384
385 val = pru_control_read_reg(pru, PRU_CTRL_CTRL);
386 val &= ~CTRL_CTRL_EN;
387 pru_control_write_reg(pru, PRU_CTRL_CTRL, val);
388
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +0100389 /* dispose irq mapping - new firmware can provide new mapping */
390 if (pru->mapped_irq)
391 pru_dispose_irq_mapping(pru);
392
Suman Annad4ce2de2020-12-08 15:09:58 +0100393 return 0;
394}
395
396/*
397 * Convert PRU device address (data spaces only) to kernel virtual address.
398 *
399 * Each PRU has access to all data memories within the PRUSS, accessible at
400 * different ranges. So, look through both its primary and secondary Data
401 * RAMs as well as any shared Data RAM to convert a PRU device address to
402 * kernel virtual address. Data RAM0 is primary Data RAM for PRU0 and Data
403 * RAM1 is primary Data RAM for PRU1.
404 */
405static void *pru_d_da_to_va(struct pru_rproc *pru, u32 da, size_t len)
406{
407 struct pruss_mem_region dram0, dram1, shrd_ram;
408 struct pruss *pruss = pru->pruss;
409 u32 offset;
410 void *va = NULL;
411
412 if (len == 0)
413 return NULL;
414
415 dram0 = pruss->mem_regions[PRUSS_MEM_DRAM0];
416 dram1 = pruss->mem_regions[PRUSS_MEM_DRAM1];
417 /* PRU1 has its local RAM addresses reversed */
418 if (pru->id == 1)
419 swap(dram0, dram1);
420 shrd_ram = pruss->mem_regions[PRUSS_MEM_SHRD_RAM2];
421
422 if (da >= PRU_PDRAM_DA && da + len <= PRU_PDRAM_DA + dram0.size) {
423 offset = da - PRU_PDRAM_DA;
424 va = (__force void *)(dram0.va + offset);
425 } else if (da >= PRU_SDRAM_DA &&
426 da + len <= PRU_SDRAM_DA + dram1.size) {
427 offset = da - PRU_SDRAM_DA;
428 va = (__force void *)(dram1.va + offset);
429 } else if (da >= PRU_SHRDRAM_DA &&
430 da + len <= PRU_SHRDRAM_DA + shrd_ram.size) {
431 offset = da - PRU_SHRDRAM_DA;
432 va = (__force void *)(shrd_ram.va + offset);
433 }
434
435 return va;
436}
437
438/*
439 * Convert PRU device address (instruction space) to kernel virtual address.
440 *
441 * A PRU does not have an unified address space. Each PRU has its very own
442 * private Instruction RAM, and its device address is identical to that of
443 * its primary Data RAM device address.
444 */
445static void *pru_i_da_to_va(struct pru_rproc *pru, u32 da, size_t len)
446{
447 u32 offset;
448 void *va = NULL;
449
450 if (len == 0)
451 return NULL;
452
Dimitar Dimitrove6d94232020-12-30 12:50:05 +0200453 /*
454 * GNU binutils do not support multiple address spaces. The GNU
455 * linker's default linker script places IRAM at an arbitrary high
456 * offset, in order to differentiate it from DRAM. Hence we need to
457 * strip the artificial offset in the IRAM addresses coming from the
458 * ELF file.
459 *
460 * The TI proprietary linker would never set those higher IRAM address
461 * bits anyway. PRU architecture limits the program counter to 16-bit
462 * word-address range. This in turn corresponds to 18-bit IRAM
463 * byte-address range for ELF.
464 *
465 * Two more bits are added just in case to make the final 20-bit mask.
466 * Idea is to have a safeguard in case TI decides to add banking
467 * in future SoCs.
468 */
469 da &= 0xfffff;
470
Suman Annad4ce2de2020-12-08 15:09:58 +0100471 if (da >= PRU_IRAM_DA &&
472 da + len <= PRU_IRAM_DA + pru->mem_regions[PRU_IOMEM_IRAM].size) {
473 offset = da - PRU_IRAM_DA;
474 va = (__force void *)(pru->mem_regions[PRU_IOMEM_IRAM].va +
475 offset);
476 }
477
478 return va;
479}
480
481/*
482 * Provide address translations for only PRU Data RAMs through the remoteproc
483 * core for any PRU client drivers. The PRU Instruction RAM access is restricted
484 * only to the PRU loader code.
485 */
486static void *pru_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len)
487{
488 struct pru_rproc *pru = rproc->priv;
489
490 return pru_d_da_to_va(pru, da, len);
491}
492
493/* PRU-specific address translator used by PRU loader. */
494static void *pru_da_to_va(struct rproc *rproc, u64 da, size_t len, bool is_iram)
495{
496 struct pru_rproc *pru = rproc->priv;
497 void *va;
498
499 if (is_iram)
500 va = pru_i_da_to_va(pru, da, len);
501 else
502 va = pru_d_da_to_va(pru, da, len);
503
504 return va;
505}
506
507static struct rproc_ops pru_rproc_ops = {
508 .start = pru_rproc_start,
509 .stop = pru_rproc_stop,
510 .da_to_va = pru_rproc_da_to_va,
511};
512
Suman Anna1d39f4d2020-12-08 15:10:01 +0100513/*
514 * Custom memory copy implementation for ICSSG PRU/RTU/Tx_PRU Cores
515 *
516 * The ICSSG PRU/RTU/Tx_PRU cores have a memory copying issue with IRAM
517 * memories, that is not seen on previous generation SoCs. The data is reflected
518 * properly in the IRAM memories only for integer (4-byte) copies. Any unaligned
519 * copies result in all the other pre-existing bytes zeroed out within that
520 * 4-byte boundary, thereby resulting in wrong text/code in the IRAMs. Also, the
521 * IRAM memory port interface does not allow any 8-byte copies (as commonly used
522 * by ARM64 memcpy implementation) and throws an exception. The DRAM memory
523 * ports do not show this behavior.
524 */
525static int pru_rproc_memcpy(void *dest, const void *src, size_t count)
526{
527 const u32 *s = src;
528 u32 *d = dest;
529 size_t size = count / 4;
530 u32 *tmp_src = NULL;
531
532 /*
533 * TODO: relax limitation of 4-byte aligned dest addresses and copy
534 * sizes
535 */
536 if ((long)dest % 4 || count % 4)
537 return -EINVAL;
538
539 /* src offsets in ELF firmware image can be non-aligned */
540 if ((long)src % 4) {
541 tmp_src = kmemdup(src, count, GFP_KERNEL);
542 if (!tmp_src)
543 return -ENOMEM;
544 s = tmp_src;
545 }
546
547 while (size--)
548 *d++ = *s++;
549
550 kfree(tmp_src);
551
552 return 0;
553}
554
Suman Annad4ce2de2020-12-08 15:09:58 +0100555static int
556pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw)
557{
Suman Anna1d39f4d2020-12-08 15:10:01 +0100558 struct pru_rproc *pru = rproc->priv;
Suman Annad4ce2de2020-12-08 15:09:58 +0100559 struct device *dev = &rproc->dev;
560 struct elf32_hdr *ehdr;
561 struct elf32_phdr *phdr;
562 int i, ret = 0;
563 const u8 *elf_data = fw->data;
564
565 ehdr = (struct elf32_hdr *)elf_data;
566 phdr = (struct elf32_phdr *)(elf_data + ehdr->e_phoff);
567
568 /* go through the available ELF segments */
569 for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
570 u32 da = phdr->p_paddr;
571 u32 memsz = phdr->p_memsz;
572 u32 filesz = phdr->p_filesz;
573 u32 offset = phdr->p_offset;
574 bool is_iram;
575 void *ptr;
576
577 if (phdr->p_type != PT_LOAD || !filesz)
578 continue;
579
580 dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x\n",
581 phdr->p_type, da, memsz, filesz);
582
583 if (filesz > memsz) {
584 dev_err(dev, "bad phdr filesz 0x%x memsz 0x%x\n",
585 filesz, memsz);
586 ret = -EINVAL;
587 break;
588 }
589
590 if (offset + filesz > fw->size) {
591 dev_err(dev, "truncated fw: need 0x%x avail 0x%zx\n",
592 offset + filesz, fw->size);
593 ret = -EINVAL;
594 break;
595 }
596
597 /* grab the kernel address for this device address */
598 is_iram = phdr->p_flags & PF_X;
599 ptr = pru_da_to_va(rproc, da, memsz, is_iram);
600 if (!ptr) {
601 dev_err(dev, "bad phdr da 0x%x mem 0x%x\n", da, memsz);
602 ret = -EINVAL;
603 break;
604 }
605
Suman Anna1d39f4d2020-12-08 15:10:01 +0100606 if (pru->data->is_k3 && is_iram) {
607 ret = pru_rproc_memcpy(ptr, elf_data + phdr->p_offset,
608 filesz);
609 if (ret) {
610 dev_err(dev, "PRU memory copy failed for da 0x%x memsz 0x%x\n",
611 da, memsz);
612 break;
613 }
614 } else {
615 memcpy(ptr, elf_data + phdr->p_offset, filesz);
616 }
Suman Annad4ce2de2020-12-08 15:09:58 +0100617
618 /* skip the memzero logic performed by remoteproc ELF loader */
619 }
620
621 return ret;
622}
623
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +0100624static const void *
625pru_rproc_find_interrupt_map(struct device *dev, const struct firmware *fw)
626{
627 struct elf32_shdr *shdr, *name_table_shdr;
628 const char *name_table;
629 const u8 *elf_data = fw->data;
630 struct elf32_hdr *ehdr = (struct elf32_hdr *)elf_data;
631 u16 shnum = ehdr->e_shnum;
632 u16 shstrndx = ehdr->e_shstrndx;
633 int i;
634
635 /* first, get the section header */
636 shdr = (struct elf32_shdr *)(elf_data + ehdr->e_shoff);
637 /* compute name table section header entry in shdr array */
638 name_table_shdr = shdr + shstrndx;
639 /* finally, compute the name table section address in elf */
640 name_table = elf_data + name_table_shdr->sh_offset;
641
642 for (i = 0; i < shnum; i++, shdr++) {
643 u32 size = shdr->sh_size;
644 u32 offset = shdr->sh_offset;
645 u32 name = shdr->sh_name;
646
647 if (strcmp(name_table + name, ".pru_irq_map"))
648 continue;
649
650 /* make sure we have the entire irq map */
651 if (offset + size > fw->size || offset + size < size) {
652 dev_err(dev, ".pru_irq_map section truncated\n");
653 return ERR_PTR(-EINVAL);
654 }
655
656 /* make sure irq map has at least the header */
657 if (sizeof(struct pru_irq_rsc) > size) {
658 dev_err(dev, "header-less .pru_irq_map section\n");
659 return ERR_PTR(-EINVAL);
660 }
661
662 return shdr;
663 }
664
665 dev_dbg(dev, "no .pru_irq_map section found for this fw\n");
666
667 return NULL;
668}
669
Suman Annad4ce2de2020-12-08 15:09:58 +0100670/*
671 * Use a custom parse_fw callback function for dealing with PRU firmware
672 * specific sections.
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +0100673 *
674 * The firmware blob can contain optional ELF sections: .resource_table section
675 * and .pru_irq_map one. The second one contains the PRUSS interrupt mapping
676 * description, which needs to be setup before powering on the PRU core. To
677 * avoid RAM wastage this ELF section is not mapped to any ELF segment (by the
678 * firmware linker) and therefore is not loaded to PRU memory.
Suman Annad4ce2de2020-12-08 15:09:58 +0100679 */
680static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
681{
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +0100682 struct device *dev = &rproc->dev;
683 struct pru_rproc *pru = rproc->priv;
684 const u8 *elf_data = fw->data;
685 const void *shdr;
686 u8 class = fw_elf_get_class(fw);
687 u64 sh_offset;
Suman Annad4ce2de2020-12-08 15:09:58 +0100688 int ret;
689
690 /* load optional rsc table */
691 ret = rproc_elf_load_rsc_table(rproc, fw);
692 if (ret == -EINVAL)
693 dev_dbg(&rproc->dev, "no resource table found for this fw\n");
694 else if (ret)
695 return ret;
696
Grzegorz Jaszczykc75c9fd2020-12-08 15:09:59 +0100697 /* find .pru_interrupt_map section, not having it is not an error */
698 shdr = pru_rproc_find_interrupt_map(dev, fw);
699 if (IS_ERR(shdr))
700 return PTR_ERR(shdr);
701
702 if (!shdr)
703 return 0;
704
705 /* preserve pointer to PRU interrupt map together with it size */
706 sh_offset = elf_shdr_get_sh_offset(class, shdr);
707 pru->pru_interrupt_map = (struct pru_irq_rsc *)(elf_data + sh_offset);
708 pru->pru_interrupt_map_sz = elf_shdr_get_sh_size(class, shdr);
709
Suman Annad4ce2de2020-12-08 15:09:58 +0100710 return 0;
711}
712
713/*
714 * Compute PRU id based on the IRAM addresses. The PRU IRAMs are
715 * always at a particular offset within the PRUSS address space.
716 */
717static int pru_rproc_set_id(struct pru_rproc *pru)
718{
719 int ret = 0;
720
721 switch (pru->mem_regions[PRU_IOMEM_IRAM].pa & PRU_IRAM_ADDR_MASK) {
Suman Anna1d39f4d2020-12-08 15:10:01 +0100722 case TX_PRU0_IRAM_ADDR_MASK:
723 fallthrough;
724 case RTU0_IRAM_ADDR_MASK:
725 fallthrough;
Suman Annad4ce2de2020-12-08 15:09:58 +0100726 case PRU0_IRAM_ADDR_MASK:
727 pru->id = 0;
728 break;
Suman Anna1d39f4d2020-12-08 15:10:01 +0100729 case TX_PRU1_IRAM_ADDR_MASK:
730 fallthrough;
731 case RTU1_IRAM_ADDR_MASK:
732 fallthrough;
Suman Annad4ce2de2020-12-08 15:09:58 +0100733 case PRU1_IRAM_ADDR_MASK:
734 pru->id = 1;
735 break;
736 default:
737 ret = -EINVAL;
738 }
739
740 return ret;
741}
742
743static int pru_rproc_probe(struct platform_device *pdev)
744{
745 struct device *dev = &pdev->dev;
746 struct device_node *np = dev->of_node;
747 struct platform_device *ppdev = to_platform_device(dev->parent);
748 struct pru_rproc *pru;
749 const char *fw_name;
750 struct rproc *rproc = NULL;
751 struct resource *res;
752 int i, ret;
Suman Anna1d39f4d2020-12-08 15:10:01 +0100753 const struct pru_private_data *data;
Suman Annad4ce2de2020-12-08 15:09:58 +0100754 const char *mem_names[PRU_IOMEM_MAX] = { "iram", "control", "debug" };
755
Suman Anna1d39f4d2020-12-08 15:10:01 +0100756 data = of_device_get_match_data(&pdev->dev);
757 if (!data)
758 return -ENODEV;
759
Suman Annad4ce2de2020-12-08 15:09:58 +0100760 ret = of_property_read_string(np, "firmware-name", &fw_name);
761 if (ret) {
762 dev_err(dev, "unable to retrieve firmware-name %d\n", ret);
763 return ret;
764 }
765
766 rproc = devm_rproc_alloc(dev, pdev->name, &pru_rproc_ops, fw_name,
767 sizeof(*pru));
768 if (!rproc) {
769 dev_err(dev, "rproc_alloc failed\n");
770 return -ENOMEM;
771 }
772 /* use a custom load function to deal with PRU-specific quirks */
773 rproc->ops->load = pru_rproc_load_elf_segments;
774
775 /* use a custom parse function to deal with PRU-specific resources */
776 rproc->ops->parse_fw = pru_rproc_parse_fw;
777
778 /* error recovery is not supported for PRUs */
779 rproc->recovery_disabled = true;
780
781 /*
782 * rproc_add will auto-boot the processor normally, but this is not
783 * desired with PRU client driven boot-flow methodology. A PRU
784 * application/client driver will boot the corresponding PRU
785 * remote-processor as part of its state machine either through the
786 * remoteproc sysfs interface or through the equivalent kernel API.
787 */
788 rproc->auto_boot = false;
789
790 pru = rproc->priv;
791 pru->dev = dev;
Suman Anna1d39f4d2020-12-08 15:10:01 +0100792 pru->data = data;
Suman Annad4ce2de2020-12-08 15:09:58 +0100793 pru->pruss = platform_get_drvdata(ppdev);
794 pru->rproc = rproc;
795 pru->fw_name = fw_name;
796
797 for (i = 0; i < ARRAY_SIZE(mem_names); i++) {
798 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
799 mem_names[i]);
800 pru->mem_regions[i].va = devm_ioremap_resource(dev, res);
801 if (IS_ERR(pru->mem_regions[i].va)) {
802 dev_err(dev, "failed to parse and map memory resource %d %s\n",
803 i, mem_names[i]);
804 ret = PTR_ERR(pru->mem_regions[i].va);
805 return ret;
806 }
807 pru->mem_regions[i].pa = res->start;
808 pru->mem_regions[i].size = resource_size(res);
809
810 dev_dbg(dev, "memory %8s: pa %pa size 0x%zx va %pK\n",
811 mem_names[i], &pru->mem_regions[i].pa,
812 pru->mem_regions[i].size, pru->mem_regions[i].va);
813 }
814
815 ret = pru_rproc_set_id(pru);
816 if (ret < 0)
817 return ret;
818
819 platform_set_drvdata(pdev, rproc);
820
821 ret = devm_rproc_add(dev, pru->rproc);
822 if (ret) {
823 dev_err(dev, "rproc_add failed: %d\n", ret);
824 return ret;
825 }
826
Suman Anna20ad1de2020-12-08 15:10:00 +0100827 pru_rproc_create_debug_entries(rproc);
828
Suman Annad4ce2de2020-12-08 15:09:58 +0100829 dev_dbg(dev, "PRU rproc node %pOF probed successfully\n", np);
830
831 return 0;
832}
833
834static int pru_rproc_remove(struct platform_device *pdev)
835{
836 struct device *dev = &pdev->dev;
837 struct rproc *rproc = platform_get_drvdata(pdev);
838
839 dev_dbg(dev, "%s: removing rproc %s\n", __func__, rproc->name);
840
841 return 0;
842}
843
Suman Anna1d39f4d2020-12-08 15:10:01 +0100844static const struct pru_private_data pru_data = {
845 .type = PRU_TYPE_PRU,
846};
847
848static const struct pru_private_data k3_pru_data = {
849 .type = PRU_TYPE_PRU,
850 .is_k3 = 1,
851};
852
853static const struct pru_private_data k3_rtu_data = {
854 .type = PRU_TYPE_RTU,
855 .is_k3 = 1,
856};
857
858static const struct pru_private_data k3_tx_pru_data = {
859 .type = PRU_TYPE_TX_PRU,
860 .is_k3 = 1,
861};
862
Suman Annad4ce2de2020-12-08 15:09:58 +0100863static const struct of_device_id pru_rproc_match[] = {
Suman Anna1d39f4d2020-12-08 15:10:01 +0100864 { .compatible = "ti,am3356-pru", .data = &pru_data },
865 { .compatible = "ti,am4376-pru", .data = &pru_data },
866 { .compatible = "ti,am5728-pru", .data = &pru_data },
867 { .compatible = "ti,k2g-pru", .data = &pru_data },
868 { .compatible = "ti,am654-pru", .data = &k3_pru_data },
869 { .compatible = "ti,am654-rtu", .data = &k3_rtu_data },
870 { .compatible = "ti,am654-tx-pru", .data = &k3_tx_pru_data },
Suman Annab44786c2020-12-08 15:10:02 +0100871 { .compatible = "ti,j721e-pru", .data = &k3_pru_data },
872 { .compatible = "ti,j721e-rtu", .data = &k3_rtu_data },
873 { .compatible = "ti,j721e-tx-pru", .data = &k3_tx_pru_data },
Suman Annad4ce2de2020-12-08 15:09:58 +0100874 {},
875};
876MODULE_DEVICE_TABLE(of, pru_rproc_match);
877
878static struct platform_driver pru_rproc_driver = {
879 .driver = {
880 .name = "pru-rproc",
881 .of_match_table = pru_rproc_match,
882 .suppress_bind_attrs = true,
883 },
884 .probe = pru_rproc_probe,
885 .remove = pru_rproc_remove,
886};
887module_platform_driver(pru_rproc_driver);
888
889MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
890MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
891MODULE_AUTHOR("Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>");
892MODULE_DESCRIPTION("PRU-ICSS Remote Processor Driver");
893MODULE_LICENSE("GPL v2");