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Thomas Gleixnera10e7632019-05-31 01:09:32 -07001// SPDX-License-Identifier: GPL-2.0-only
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -03002/*
3 * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -03004 */
5
6#include <linux/clk.h>
7#include <linux/err.h>
8#include <linux/io.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_address.h>
13#include <linux/platform_device.h>
14#include <linux/pwm.h>
15#include <linux/slab.h>
16
17struct lpc32xx_pwm_chip {
18 struct pwm_chip chip;
19 struct clk *clk;
20 void __iomem *base;
21};
22
Vladimir Zapolskiy5a9fc9c2015-12-06 13:32:01 +020023#define PWM_ENABLE BIT(31)
Sylvain Lemieuxacfd92f2016-06-27 09:09:55 -040024#define PWM_PIN_LEVEL BIT(30)
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -030025
26#define to_lpc32xx_pwm_chip(_chip) \
27 container_of(_chip, struct lpc32xx_pwm_chip, chip)
28
29static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
30 int duty_ns, int period_ns)
31{
32 struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
33 unsigned long long c;
34 int period_cycles, duty_cycles;
Axel Linaffb9232013-04-23 14:02:49 +080035 u32 val;
Vladimir Zapolskiy5a9fc9c2015-12-06 13:32:01 +020036 c = clk_get_rate(lpc32xx->clk);
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -030037
Vladimir Zapolskiy5a9fc9c2015-12-06 13:32:01 +020038 /* The highest acceptable divisor is 256, which is represented by 0 */
39 period_cycles = div64_u64(c * period_ns,
40 (unsigned long long)NSEC_PER_SEC * 256);
Vladimir Zapolskiyd6dbdf02015-12-06 13:32:02 +020041 if (!period_cycles || period_cycles > 256)
42 return -ERANGE;
43 if (period_cycles == 256)
Vladimir Zapolskiy5a9fc9c2015-12-06 13:32:01 +020044 period_cycles = 0;
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -030045
Vladimir Zapolskiy5a9fc9c2015-12-06 13:32:01 +020046 /* Compute 256 x #duty/period value and care for corner cases */
47 duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
48 period_ns);
49 if (!duty_cycles)
50 duty_cycles = 1;
51 if (duty_cycles > 255)
52 duty_cycles = 255;
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -030053
Axel Linaffb9232013-04-23 14:02:49 +080054 val = readl(lpc32xx->base + (pwm->hwpwm << 2));
55 val &= ~0xFFFF;
Vladimir Zapolskiy5a9fc9c2015-12-06 13:32:01 +020056 val |= (period_cycles << 8) | duty_cycles;
Axel Linaffb9232013-04-23 14:02:49 +080057 writel(val, lpc32xx->base + (pwm->hwpwm << 2));
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -030058
59 return 0;
60}
61
62static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
63{
64 struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
Axel Lin08ee77b2013-04-23 14:01:31 +080065 u32 val;
66 int ret;
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -030067
Vladimir Zapolskiy82aff042015-12-06 13:32:00 +020068 ret = clk_prepare_enable(lpc32xx->clk);
Axel Lin08ee77b2013-04-23 14:01:31 +080069 if (ret)
70 return ret;
71
72 val = readl(lpc32xx->base + (pwm->hwpwm << 2));
73 val |= PWM_ENABLE;
74 writel(val, lpc32xx->base + (pwm->hwpwm << 2));
75
76 return 0;
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -030077}
78
79static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
80{
81 struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
Axel Lin08ee77b2013-04-23 14:01:31 +080082 u32 val;
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -030083
Axel Lin08ee77b2013-04-23 14:01:31 +080084 val = readl(lpc32xx->base + (pwm->hwpwm << 2));
85 val &= ~PWM_ENABLE;
86 writel(val, lpc32xx->base + (pwm->hwpwm << 2));
87
Vladimir Zapolskiy82aff042015-12-06 13:32:00 +020088 clk_disable_unprepare(lpc32xx->clk);
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -030089}
90
91static const struct pwm_ops lpc32xx_pwm_ops = {
92 .config = lpc32xx_pwm_config,
93 .enable = lpc32xx_pwm_enable,
94 .disable = lpc32xx_pwm_disable,
95 .owner = THIS_MODULE,
96};
97
98static int lpc32xx_pwm_probe(struct platform_device *pdev)
99{
100 struct lpc32xx_pwm_chip *lpc32xx;
101 struct resource *res;
102 int ret;
Sylvain Lemieuxacfd92f2016-06-27 09:09:55 -0400103 u32 val;
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -0300104
105 lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
106 if (!lpc32xx)
107 return -ENOMEM;
108
109 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding6d4294d2013-01-21 11:09:16 +0100110 lpc32xx->base = devm_ioremap_resource(&pdev->dev, res);
111 if (IS_ERR(lpc32xx->base))
112 return PTR_ERR(lpc32xx->base);
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -0300113
114 lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
115 if (IS_ERR(lpc32xx->clk))
116 return PTR_ERR(lpc32xx->clk);
117
118 lpc32xx->chip.dev = &pdev->dev;
119 lpc32xx->chip.ops = &lpc32xx_pwm_ops;
Vladimir Zapolskiyebe1fca2015-12-06 13:31:59 +0200120 lpc32xx->chip.npwm = 1;
Alban Bedel8fc6d092012-11-14 12:58:15 +0100121 lpc32xx->chip.base = -1;
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -0300122
123 ret = pwmchip_add(&lpc32xx->chip);
124 if (ret < 0) {
125 dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
126 return ret;
127 }
128
Sylvain Lemieuxacfd92f2016-06-27 09:09:55 -0400129 /* When PWM is disable, configure the output to the default value */
130 val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
131 val &= ~PWM_PIN_LEVEL;
132 writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
133
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -0300134 platform_set_drvdata(pdev, lpc32xx);
135
136 return 0;
137}
138
Bill Pemberton77f37912012-11-19 13:26:09 -0500139static int lpc32xx_pwm_remove(struct platform_device *pdev)
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -0300140{
141 struct lpc32xx_pwm_chip *lpc32xx = platform_get_drvdata(pdev);
Alban Bedel54b2a992012-11-14 12:58:14 +0100142 unsigned int i;
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -0300143
Alban Bedel54b2a992012-11-14 12:58:14 +0100144 for (i = 0; i < lpc32xx->chip.npwm; i++)
145 pwm_disable(&lpc32xx->chip.pwms[i]);
146
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -0300147 return pwmchip_remove(&lpc32xx->chip);
148}
149
Thierry Redingf1a88702013-04-18 10:04:14 +0200150static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -0300151 { .compatible = "nxp,lpc3220-pwm", },
152 { /* sentinel */ }
153};
154MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
155
156static struct platform_driver lpc32xx_pwm_driver = {
157 .driver = {
158 .name = "lpc32xx-pwm",
Sachin Kamat3cb3b2b2013-09-30 08:56:40 +0530159 .of_match_table = lpc32xx_pwm_dt_ids,
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -0300160 },
161 .probe = lpc32xx_pwm_probe,
Bill Pembertonfd109112012-11-19 13:21:28 -0500162 .remove = lpc32xx_pwm_remove,
Alexandre Pereira da Silva2132fa82012-07-10 11:38:10 -0300163};
164module_platform_driver(lpc32xx_pwm_driver);
165
166MODULE_ALIAS("platform:lpc32xx-pwm");
167MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
168MODULE_DESCRIPTION("LPC32XX PWM Driver");
169MODULE_LICENSE("GPL v2");