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Catalin Marinasb3901d52012-03-05 11:49:28 +00001/*
2 * Based on arch/arm/kernel/process.c
3 *
4 * Original Copyright (C) 1995 Linus Torvalds
5 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <stdarg.h>
22
AKASHI Takahirofd92d4a2014-04-30 10:51:32 +010023#include <linux/compat.h>
Ard Biesheuvel60c0d452015-03-06 15:49:24 +010024#include <linux/efi.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000025#include <linux/export.h>
26#include <linux/sched.h>
Ingo Molnarb17b0152017-02-08 18:51:35 +010027#include <linux/sched/debug.h>
Ingo Molnar29930022017-02-08 18:51:36 +010028#include <linux/sched/task.h>
Ingo Molnar68db0cf2017-02-08 18:51:37 +010029#include <linux/sched/task_stack.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000030#include <linux/kernel.h>
31#include <linux/mm.h>
32#include <linux/stddef.h>
33#include <linux/unistd.h>
34#include <linux/user.h>
35#include <linux/delay.h>
36#include <linux/reboot.h>
37#include <linux/interrupt.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000038#include <linux/init.h>
39#include <linux/cpu.h>
40#include <linux/elfcore.h>
41#include <linux/pm.h>
42#include <linux/tick.h>
43#include <linux/utsname.h>
44#include <linux/uaccess.h>
45#include <linux/random.h>
46#include <linux/hw_breakpoint.h>
47#include <linux/personality.h>
48#include <linux/notifier.h>
Jisheng Zhang096b3222015-09-16 22:23:21 +080049#include <trace/events/power.h>
Mark Rutlandc02433d2016-11-03 20:23:13 +000050#include <linux/percpu.h>
Dave Martinbc0ee472017-10-31 15:51:05 +000051#include <linux/thread_info.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000052
James Morse57f49592016-02-05 14:58:48 +000053#include <asm/alternative.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000054#include <asm/compat.h>
55#include <asm/cacheflush.h>
James Morsed0854412016-10-18 11:27:48 +010056#include <asm/exec.h>
Will Deaconec45d1c2013-01-17 12:31:45 +000057#include <asm/fpsimd.h>
58#include <asm/mmu_context.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000059#include <asm/processor.h>
60#include <asm/stacktrace.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000061
Laura Abbottc0c264a2014-06-25 23:55:03 +010062#ifdef CONFIG_CC_STACKPROTECTOR
63#include <linux/stackprotector.h>
64unsigned long __stack_chk_guard __read_mostly;
65EXPORT_SYMBOL(__stack_chk_guard);
66#endif
67
Catalin Marinasb3901d52012-03-05 11:49:28 +000068/*
69 * Function pointers to optional machine specific functions
70 */
71void (*pm_power_off)(void);
72EXPORT_SYMBOL_GPL(pm_power_off);
73
Catalin Marinasb0946fc2013-07-23 11:05:10 +010074void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
Catalin Marinasb3901d52012-03-05 11:49:28 +000075
Catalin Marinasb3901d52012-03-05 11:49:28 +000076/*
77 * This is our default idle handler.
78 */
Thomas Gleixner00872982013-03-21 22:49:39 +010079void arch_cpu_idle(void)
Catalin Marinasb3901d52012-03-05 11:49:28 +000080{
81 /*
82 * This should do all the clock switching and wait for interrupt
83 * tricks
84 */
Jisheng Zhang096b3222015-09-16 22:23:21 +080085 trace_cpu_idle_rcuidle(1, smp_processor_id());
Nicolas Pitre69905662014-02-17 10:59:30 -050086 cpu_do_idle();
87 local_irq_enable();
Jisheng Zhang096b3222015-09-16 22:23:21 +080088 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
Catalin Marinasb3901d52012-03-05 11:49:28 +000089}
90
Mark Rutland9327e2c2013-10-24 20:30:18 +010091#ifdef CONFIG_HOTPLUG_CPU
92void arch_cpu_idle_dead(void)
93{
94 cpu_die();
95}
96#endif
97
Arun KS90f51a02014-05-07 02:41:22 +010098/*
99 * Called by kexec, immediately prior to machine_kexec().
100 *
101 * This must completely disable all secondary CPUs; simply causing those CPUs
102 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
103 * kexec'd kernel to use any and all RAM as it sees fit, without having to
104 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
105 * functionality embodied in disable_nonboot_cpus() to achieve this.
106 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000107void machine_shutdown(void)
108{
Arun KS90f51a02014-05-07 02:41:22 +0100109 disable_nonboot_cpus();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000110}
111
Arun KS90f51a02014-05-07 02:41:22 +0100112/*
113 * Halting simply requires that the secondary CPUs stop performing any
114 * activity (executing tasks, handling interrupts). smp_send_stop()
115 * achieves this.
116 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000117void machine_halt(void)
118{
Arun KSb9acc492014-05-07 02:41:23 +0100119 local_irq_disable();
Arun KS90f51a02014-05-07 02:41:22 +0100120 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000121 while (1);
122}
123
Arun KS90f51a02014-05-07 02:41:22 +0100124/*
125 * Power-off simply requires that the secondary CPUs stop performing any
126 * activity (executing tasks, handling interrupts). smp_send_stop()
127 * achieves this. When the system power is turned off, it will take all CPUs
128 * with it.
129 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000130void machine_power_off(void)
131{
Arun KSb9acc492014-05-07 02:41:23 +0100132 local_irq_disable();
Arun KS90f51a02014-05-07 02:41:22 +0100133 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000134 if (pm_power_off)
135 pm_power_off();
136}
137
Arun KS90f51a02014-05-07 02:41:22 +0100138/*
139 * Restart requires that the secondary CPUs stop performing any activity
Mark Rutland68234df2015-04-20 10:24:35 +0100140 * while the primary CPU resets the system. Systems with multiple CPUs must
Arun KS90f51a02014-05-07 02:41:22 +0100141 * provide a HW restart implementation, to ensure that all CPUs reset at once.
142 * This is required so that any code running after reset on the primary CPU
143 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
144 * executing pre-reset code, and using RAM that the primary CPU's code wishes
145 * to use. Implementing such co-ordination would be essentially impossible.
146 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000147void machine_restart(char *cmd)
148{
Catalin Marinasb3901d52012-03-05 11:49:28 +0000149 /* Disable interrupts first */
150 local_irq_disable();
Arun KSb9acc492014-05-07 02:41:23 +0100151 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000152
Ard Biesheuvel60c0d452015-03-06 15:49:24 +0100153 /*
154 * UpdateCapsule() depends on the system being reset via
155 * ResetSystem().
156 */
157 if (efi_enabled(EFI_RUNTIME_SERVICES))
158 efi_reboot(reboot_mode, NULL);
159
Catalin Marinasb3901d52012-03-05 11:49:28 +0000160 /* Now call the architecture specific reboot code. */
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000161 if (arm_pm_restart)
Marc Zyngierff701302013-07-11 12:13:00 +0100162 arm_pm_restart(reboot_mode, cmd);
Guenter Roeck1c7ffc32014-09-26 00:03:16 +0000163 else
164 do_kernel_restart(cmd);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000165
166 /*
167 * Whoops - the architecture was unable to reboot.
168 */
169 printk("Reboot failed -- System halted\n");
170 while (1);
171}
172
Will Deaconb7300d42017-10-19 13:26:26 +0100173static void print_pstate(struct pt_regs *regs)
174{
175 u64 pstate = regs->pstate;
176
177 if (compat_user_mode(regs)) {
178 printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c)\n",
179 pstate,
180 pstate & COMPAT_PSR_N_BIT ? 'N' : 'n',
181 pstate & COMPAT_PSR_Z_BIT ? 'Z' : 'z',
182 pstate & COMPAT_PSR_C_BIT ? 'C' : 'c',
183 pstate & COMPAT_PSR_V_BIT ? 'V' : 'v',
184 pstate & COMPAT_PSR_Q_BIT ? 'Q' : 'q',
185 pstate & COMPAT_PSR_T_BIT ? "T32" : "A32",
186 pstate & COMPAT_PSR_E_BIT ? "BE" : "LE",
187 pstate & COMPAT_PSR_A_BIT ? 'A' : 'a',
188 pstate & COMPAT_PSR_I_BIT ? 'I' : 'i',
189 pstate & COMPAT_PSR_F_BIT ? 'F' : 'f');
190 } else {
191 printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO)\n",
192 pstate,
193 pstate & PSR_N_BIT ? 'N' : 'n',
194 pstate & PSR_Z_BIT ? 'Z' : 'z',
195 pstate & PSR_C_BIT ? 'C' : 'c',
196 pstate & PSR_V_BIT ? 'V' : 'v',
197 pstate & PSR_D_BIT ? 'D' : 'd',
198 pstate & PSR_A_BIT ? 'A' : 'a',
199 pstate & PSR_I_BIT ? 'I' : 'i',
200 pstate & PSR_F_BIT ? 'F' : 'f',
201 pstate & PSR_PAN_BIT ? '+' : '-',
202 pstate & PSR_UAO_BIT ? '+' : '-');
203 }
204}
205
Catalin Marinasb3901d52012-03-05 11:49:28 +0000206void __show_regs(struct pt_regs *regs)
207{
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100208 int i, top_reg;
209 u64 lr, sp;
210
211 if (compat_user_mode(regs)) {
212 lr = regs->compat_lr;
213 sp = regs->compat_sp;
214 top_reg = 12;
215 } else {
216 lr = regs->regs[30];
217 sp = regs->sp;
218 top_reg = 29;
219 }
Catalin Marinasb3901d52012-03-05 11:49:28 +0000220
Tejun Heoa43cb952013-04-30 15:27:17 -0700221 show_regs_print_info(KERN_DEFAULT);
Will Deaconb7300d42017-10-19 13:26:26 +0100222 print_pstate(regs);
Will Deacona06f8182018-02-19 16:46:57 +0000223
224 if (!user_mode(regs)) {
225 printk("pc : %pS\n", (void *)regs->pc);
226 printk("lr : %pS\n", (void *)lr);
227 } else {
228 printk("pc : %016llx\n", regs->pc);
229 printk("lr : %016llx\n", lr);
230 }
231
Will Deaconb7300d42017-10-19 13:26:26 +0100232 printk("sp : %016llx\n", sp);
Mark Rutlanddb4b0712016-10-20 12:23:16 +0100233
234 i = top_reg;
235
236 while (i >= 0) {
Catalin Marinasb3901d52012-03-05 11:49:28 +0000237 printk("x%-2d: %016llx ", i, regs->regs[i]);
Mark Rutlanddb4b0712016-10-20 12:23:16 +0100238 i--;
239
240 if (i % 2 == 0) {
241 pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
242 i--;
243 }
244
245 pr_cont("\n");
Catalin Marinasb3901d52012-03-05 11:49:28 +0000246 }
Catalin Marinasb3901d52012-03-05 11:49:28 +0000247}
248
249void show_regs(struct pt_regs * regs)
250{
Catalin Marinasb3901d52012-03-05 11:49:28 +0000251 __show_regs(regs);
Kefeng Wang1149aad2017-05-09 09:53:37 +0800252 dump_backtrace(regs, NULL);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000253}
254
Will Deaconeb35bdd72014-09-11 14:38:16 +0100255static void tls_thread_flush(void)
256{
Mark Rutlandadf75892016-09-08 13:55:38 +0100257 write_sysreg(0, tpidr_el0);
Will Deaconeb35bdd72014-09-11 14:38:16 +0100258
259 if (is_compat_task()) {
260 current->thread.tp_value = 0;
261
262 /*
263 * We need to ensure ordering between the shadow state and the
264 * hardware state, so that we don't corrupt the hardware state
265 * with a stale shadow state during context switch.
266 */
267 barrier();
Mark Rutlandadf75892016-09-08 13:55:38 +0100268 write_sysreg(0, tpidrro_el0);
Will Deaconeb35bdd72014-09-11 14:38:16 +0100269 }
270}
271
Catalin Marinasb3901d52012-03-05 11:49:28 +0000272void flush_thread(void)
273{
274 fpsimd_flush_thread();
Will Deaconeb35bdd72014-09-11 14:38:16 +0100275 tls_thread_flush();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000276 flush_ptrace_hw_breakpoint(current);
277}
278
279void release_thread(struct task_struct *dead_task)
280{
281}
282
Dave Martinbc0ee472017-10-31 15:51:05 +0000283void arch_release_task_struct(struct task_struct *tsk)
284{
285 fpsimd_release_task(tsk);
286}
287
288/*
289 * src and dst may temporarily have aliased sve_state after task_struct
290 * is copied. We cannot fix this properly here, because src may have
291 * live SVE state and dst's thread_info may not exist yet, so tweaking
292 * either src's or dst's TIF_SVE is not safe.
293 *
294 * The unaliasing is done in copy_thread() instead. This works because
295 * dst is not schedulable or traceable until both of these functions
296 * have been called.
297 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000298int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
299{
Janet Liu6eb6c802015-06-11 12:04:32 +0800300 if (current->mm)
301 fpsimd_preserve_current_state();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000302 *dst = *src;
Dave Martinbc0ee472017-10-31 15:51:05 +0000303
Catalin Marinasb3901d52012-03-05 11:49:28 +0000304 return 0;
305}
306
307asmlinkage void ret_from_fork(void) asm("ret_from_fork");
308
309int copy_thread(unsigned long clone_flags, unsigned long stack_start,
Al Viroafa86fc2012-10-22 22:51:14 -0400310 unsigned long stk_sz, struct task_struct *p)
Catalin Marinasb3901d52012-03-05 11:49:28 +0000311{
312 struct pt_regs *childregs = task_pt_regs(p);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000313
Catalin Marinasb3901d52012-03-05 11:49:28 +0000314 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
Catalin Marinasb3901d52012-03-05 11:49:28 +0000315
Dave Martinbc0ee472017-10-31 15:51:05 +0000316 /*
317 * Unalias p->thread.sve_state (if any) from the parent task
318 * and disable discard SVE state for p:
319 */
320 clear_tsk_thread_flag(p, TIF_SVE);
321 p->thread.sve_state = NULL;
322
Dave Martin071b6d42017-12-05 14:56:42 +0000323 /*
324 * In case p was allocated the same task_struct pointer as some
325 * other recently-exited task, make sure p is disassociated from
326 * any cpu that may have run that now-exited task recently.
327 * Otherwise we could erroneously skip reloading the FPSIMD
328 * registers for p.
329 */
330 fpsimd_flush_task_state(p);
331
Al Viro9ac08002012-10-21 15:56:52 -0400332 if (likely(!(p->flags & PF_KTHREAD))) {
333 *childregs = *current_pt_regs();
Catalin Marinasc34501d2012-10-05 12:31:20 +0100334 childregs->regs[0] = 0;
Will Deacond00a3812015-05-27 15:39:40 +0100335
336 /*
337 * Read the current TLS pointer from tpidr_el0 as it may be
338 * out-of-sync with the saved value.
339 */
Mark Rutlandadf75892016-09-08 13:55:38 +0100340 *task_user_tls(p) = read_sysreg(tpidr_el0);
Will Deacond00a3812015-05-27 15:39:40 +0100341
342 if (stack_start) {
343 if (is_compat_thread(task_thread_info(p)))
Al Viroe0fd18c2012-10-18 00:55:54 -0400344 childregs->compat_sp = stack_start;
Will Deacond00a3812015-05-27 15:39:40 +0100345 else
Al Viroe0fd18c2012-10-18 00:55:54 -0400346 childregs->sp = stack_start;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100347 }
Will Deacond00a3812015-05-27 15:39:40 +0100348
Catalin Marinasc34501d2012-10-05 12:31:20 +0100349 /*
350 * If a TLS pointer was passed to clone (4th argument), use it
351 * for the new thread.
352 */
353 if (clone_flags & CLONE_SETTLS)
Will Deacond00a3812015-05-27 15:39:40 +0100354 p->thread.tp_value = childregs->regs[3];
Catalin Marinasc34501d2012-10-05 12:31:20 +0100355 } else {
356 memset(childregs, 0, sizeof(struct pt_regs));
357 childregs->pstate = PSR_MODE_EL1h;
James Morse57f49592016-02-05 14:58:48 +0000358 if (IS_ENABLED(CONFIG_ARM64_UAO) &&
Suzuki K Poulosea4023f682016-11-08 13:56:20 +0000359 cpus_have_const_cap(ARM64_HAS_UAO))
James Morse57f49592016-02-05 14:58:48 +0000360 childregs->pstate |= PSR_UAO_BIT;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100361 p->thread.cpu_context.x19 = stack_start;
362 p->thread.cpu_context.x20 = stk_sz;
363 }
364 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
365 p->thread.cpu_context.sp = (unsigned long)childregs;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000366
367 ptrace_hw_copy_thread(p);
368
369 return 0;
370}
371
Dave Martin936eb652017-06-21 16:00:44 +0100372void tls_preserve_current_state(void)
373{
374 *task_user_tls(current) = read_sysreg(tpidr_el0);
375}
376
Catalin Marinasb3901d52012-03-05 11:49:28 +0000377static void tls_thread_switch(struct task_struct *next)
378{
Dave Martin936eb652017-06-21 16:00:44 +0100379 tls_preserve_current_state();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000380
Will Deacon18011ea2017-11-14 14:33:28 +0000381 if (is_compat_thread(task_thread_info(next)))
382 write_sysreg(next->thread.tp_value, tpidrro_el0);
383 else if (!arm64_kernel_unmapped_at_el0())
384 write_sysreg(0, tpidrro_el0);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000385
Will Deacon18011ea2017-11-14 14:33:28 +0000386 write_sysreg(*task_user_tls(next), tpidr_el0);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000387}
388
James Morse57f49592016-02-05 14:58:48 +0000389/* Restore the UAO state depending on next's addr_limit */
James Morsed0854412016-10-18 11:27:48 +0100390void uao_thread_switch(struct task_struct *next)
James Morse57f49592016-02-05 14:58:48 +0000391{
Catalin Marinase9506312016-02-18 15:50:04 +0000392 if (IS_ENABLED(CONFIG_ARM64_UAO)) {
393 if (task_thread_info(next)->addr_limit == KERNEL_DS)
394 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
395 else
396 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
397 }
James Morse57f49592016-02-05 14:58:48 +0000398}
399
Catalin Marinasb3901d52012-03-05 11:49:28 +0000400/*
Mark Rutlandc02433d2016-11-03 20:23:13 +0000401 * We store our current task in sp_el0, which is clobbered by userspace. Keep a
402 * shadow copy so that we can restore this upon entry from userspace.
403 *
404 * This is *only* for exception entry from EL0, and is not valid until we
405 * __switch_to() a user task.
406 */
407DEFINE_PER_CPU(struct task_struct *, __entry_task);
408
409static void entry_task_switch(struct task_struct *next)
410{
411 __this_cpu_write(__entry_task, next);
412}
413
414/*
Catalin Marinasb3901d52012-03-05 11:49:28 +0000415 * Thread switching.
416 */
Joel Fernandes8f4b3262016-12-21 14:44:46 -0800417__notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
Catalin Marinasb3901d52012-03-05 11:49:28 +0000418 struct task_struct *next)
419{
420 struct task_struct *last;
421
422 fpsimd_thread_switch(next);
423 tls_thread_switch(next);
424 hw_breakpoint_thread_switch(next);
Christopher Covington33257322013-04-03 19:01:01 +0100425 contextidr_thread_switch(next);
Mark Rutlandc02433d2016-11-03 20:23:13 +0000426 entry_task_switch(next);
James Morse57f49592016-02-05 14:58:48 +0000427 uao_thread_switch(next);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000428
Catalin Marinas5108c672013-04-24 14:47:02 +0100429 /*
430 * Complete any pending TLB or cache maintenance on this CPU in case
431 * the thread migrates to a different CPU.
Mathieu Desnoyers22e4ebb2017-07-28 16:40:40 -0400432 * This full barrier is also required by the membarrier system
433 * call.
Catalin Marinas5108c672013-04-24 14:47:02 +0100434 */
Will Deacon98f76852014-05-02 16:24:10 +0100435 dsb(ish);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000436
437 /* the actual thread switch */
438 last = cpu_switch_to(prev, next);
439
440 return last;
441}
442
Catalin Marinasb3901d52012-03-05 11:49:28 +0000443unsigned long get_wchan(struct task_struct *p)
444{
445 struct stackframe frame;
Mark Rutland9bbd4c52016-11-03 20:23:08 +0000446 unsigned long stack_page, ret = 0;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000447 int count = 0;
448 if (!p || p == current || p->state == TASK_RUNNING)
449 return 0;
450
Mark Rutland9bbd4c52016-11-03 20:23:08 +0000451 stack_page = (unsigned long)try_get_task_stack(p);
452 if (!stack_page)
453 return 0;
454
Catalin Marinasb3901d52012-03-05 11:49:28 +0000455 frame.fp = thread_saved_fp(p);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000456 frame.pc = thread_saved_pc(p);
AKASHI Takahiro20380bb2015-12-15 17:33:41 +0900457#ifdef CONFIG_FUNCTION_GRAPH_TRACER
458 frame.graph = p->curr_ret_stack;
459#endif
Catalin Marinasb3901d52012-03-05 11:49:28 +0000460 do {
Ard Biesheuvel31e43ad2017-07-23 09:05:38 +0100461 if (unwind_frame(p, &frame))
Mark Rutland9bbd4c52016-11-03 20:23:08 +0000462 goto out;
463 if (!in_sched_functions(frame.pc)) {
464 ret = frame.pc;
465 goto out;
466 }
Catalin Marinasb3901d52012-03-05 11:49:28 +0000467 } while (count ++ < 16);
Mark Rutland9bbd4c52016-11-03 20:23:08 +0000468
469out:
470 put_task_stack(p);
471 return ret;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000472}
473
474unsigned long arch_align_stack(unsigned long sp)
475{
476 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
477 sp -= get_random_int() & ~PAGE_MASK;
478 return sp & ~0xf;
479}
480
Catalin Marinasb3901d52012-03-05 11:49:28 +0000481unsigned long arch_randomize_brk(struct mm_struct *mm)
482{
Kees Cook61462c82016-05-10 10:55:49 -0700483 if (is_compat_task())
Miles Chenffe3d1e2017-02-09 09:52:03 +0800484 return randomize_page(mm->brk, SZ_32M);
Kees Cook61462c82016-05-10 10:55:49 -0700485 else
Miles Chenffe3d1e2017-02-09 09:52:03 +0800486 return randomize_page(mm->brk, SZ_1G);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000487}
Yury Norovd1be5c92017-08-20 13:20:48 +0300488
489/*
490 * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
491 */
492void arch_setup_new_exec(void)
493{
494 current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0;
495}