blob: 5ebdf1b4b8d5b24304357d049986829a71ea16c3 [file] [log] [blame]
Bjorn Helgaas8cfab3c2018-01-26 12:50:27 -06001// SPDX-License-Identifier: GPL-2.0
Xiaowei Songfc5165d2017-06-19 18:23:48 +08002/*
3 * PCIe host controller driver for Kirin Phone SoCs
4 *
Bjorn Helgaasf6b6aef2019-05-30 08:05:58 -05005 * Copyright (C) 2017 HiSilicon Electronics Co., Ltd.
Alexander A. Klimov7ecd4a82020-06-27 12:30:50 +02006 * https://www.huawei.com
Xiaowei Songfc5165d2017-06-19 18:23:48 +08007 *
8 * Author: Xiaowei Song <songxiaowei@huawei.com>
Xiaowei Songfc5165d2017-06-19 18:23:48 +08009 */
10
Xiaowei Songfc5165d2017-06-19 18:23:48 +080011#include <linux/clk.h>
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +010012#include <linux/compiler.h>
Xiaowei Songfc5165d2017-06-19 18:23:48 +080013#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/gpio.h>
16#include <linux/interrupt.h>
17#include <linux/mfd/syscon.h>
18#include <linux/of_address.h>
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +010019#include <linux/of_device.h>
Xiaowei Songfc5165d2017-06-19 18:23:48 +080020#include <linux/of_gpio.h>
21#include <linux/of_pci.h>
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +010022#include <linux/phy/phy.h>
Xiaowei Songfc5165d2017-06-19 18:23:48 +080023#include <linux/pci.h>
24#include <linux/pci_regs.h>
25#include <linux/platform_device.h>
26#include <linux/regmap.h>
27#include <linux/resource.h>
28#include <linux/types.h>
29#include "pcie-designware.h"
30
31#define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
32
Xiaowei Songfc5165d2017-06-19 18:23:48 +080033/* PCIe ELBI registers */
34#define SOC_PCIECTRL_CTRL0_ADDR 0x000
35#define SOC_PCIECTRL_CTRL1_ADDR 0x004
Xiaowei Songfc5165d2017-06-19 18:23:48 +080036#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
37
38/* info located in APB */
39#define PCIE_APP_LTSSM_ENABLE 0x01c
Xiaowei Songfc5165d2017-06-19 18:23:48 +080040#define PCIE_APB_PHY_STATUS0 0x400
41#define PCIE_LINKUP_ENABLE (0x8020)
42#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11)
Xiaowei Songfc5165d2017-06-19 18:23:48 +080043
44/* info located in sysctrl */
45#define SCTRL_PCIE_CMOS_OFFSET 0x60
46#define SCTRL_PCIE_CMOS_BIT 0x10
47#define SCTRL_PCIE_ISO_OFFSET 0x44
48#define SCTRL_PCIE_ISO_BIT 0x30
49#define SCTRL_PCIE_HPCLK_OFFSET 0x190
50#define SCTRL_PCIE_HPCLK_BIT 0x184000
51#define SCTRL_PCIE_OE_OFFSET 0x14a
52#define PCIE_DEBOUNCE_PARAM 0xF0F400
53#define PCIE_OE_BYPASS (0x3 << 28)
54
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +010055/*
56 * Max number of connected PCI slots at an external PCI bridge
57 *
58 * This is used on HiKey 970, which has a PEX 8606 bridge with 4 connected
59 * lanes (lane 0 upstream, and the other three lanes, one connected to an
60 * in-board Ethernet adapter and the other two connected to M.2 and mini
61 * PCI slots.
62 *
63 * Each slot has a different clock source and uses a separate PERST# pin.
64 */
65#define MAX_PCI_SLOTS 3
66
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +010067enum pcie_kirin_phy_type {
68 PCIE_KIRIN_INTERNAL_PHY,
69 PCIE_KIRIN_EXTERNAL_PHY
70};
71
Mauro Carvalho Chehab61d37542021-10-21 11:45:08 +010072struct kirin_pcie {
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +010073 enum pcie_kirin_phy_type type;
74
Mauro Carvalho Chehab61d37542021-10-21 11:45:08 +010075 struct dw_pcie *pci;
Mauro Carvalho Chehabd19afe72021-10-21 11:45:10 +010076 struct regmap *apb;
Mauro Carvalho Chehab61d37542021-10-21 11:45:08 +010077 struct phy *phy;
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +010078 void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +010079
80 /* DWC PERST# */
81 int gpio_id_dwc_perst;
82
83 /* Per-slot PERST# */
84 int num_slots;
85 int gpio_id_reset[MAX_PCI_SLOTS];
86 const char *reset_names[MAX_PCI_SLOTS];
87
88 /* Per-slot clkreq */
89 int n_gpio_clkreq;
90 int gpio_id_clkreq[MAX_PCI_SLOTS];
91 const char *clkreq_names[MAX_PCI_SLOTS];
Mauro Carvalho Chehab61d37542021-10-21 11:45:08 +010092};
93
94/*
95 * Kirin 960 PHY. Can't be split into a PHY driver without changing the
96 * DT schema.
97 */
98
99#define REF_CLK_FREQ 100000000
100
101/* PHY info located in APB */
102#define PCIE_APB_PHY_CTRL0 0x0
103#define PCIE_APB_PHY_CTRL1 0x4
104#define PCIE_APB_PHY_STATUS0 0x400
105#define PIPE_CLK_STABLE BIT(19)
106#define PHY_REF_PAD_BIT BIT(8)
107#define PHY_PWR_DOWN_BIT BIT(22)
108#define PHY_RST_ACK_BIT BIT(16)
109
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800110/* peri_crg ctrl */
111#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
112#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
113
114/* Time for delay */
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100115#define REF_2_PERST_MIN 21000
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800116#define REF_2_PERST_MAX 25000
117#define PERST_2_ACCESS_MIN 10000
118#define PERST_2_ACCESS_MAX 12000
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800119#define PIPE_CLK_WAIT_MIN 550
120#define PIPE_CLK_WAIT_MAX 600
121#define TIME_CMOS_MIN 100
122#define TIME_CMOS_MAX 105
123#define TIME_PHY_PD_MIN 10
124#define TIME_PHY_PD_MAX 11
125
Mauro Carvalho Chehab61d37542021-10-21 11:45:08 +0100126struct hi3660_pcie_phy {
127 struct device *dev;
128 void __iomem *base;
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800129 struct regmap *crgctrl;
130 struct regmap *sysctrl;
131 struct clk *apb_sys_clk;
132 struct clk *apb_phy_clk;
133 struct clk *phy_ref_clk;
Mauro Carvalho Chehab61d37542021-10-21 11:45:08 +0100134 struct clk *aclk;
135 struct clk *aux_clk;
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800136};
137
Mauro Carvalho Chehab61d37542021-10-21 11:45:08 +0100138/* Registers in PCIePHY */
139static inline void kirin_apb_phy_writel(struct hi3660_pcie_phy *hi3660_pcie_phy,
140 u32 val, u32 reg)
141{
142 writel(val, hi3660_pcie_phy->base + reg);
143}
144
145static inline u32 kirin_apb_phy_readl(struct hi3660_pcie_phy *hi3660_pcie_phy,
146 u32 reg)
147{
148 return readl(hi3660_pcie_phy->base + reg);
149}
150
151static int hi3660_pcie_phy_get_clk(struct hi3660_pcie_phy *phy)
152{
153 struct device *dev = phy->dev;
154
155 phy->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref");
156 if (IS_ERR(phy->phy_ref_clk))
157 return PTR_ERR(phy->phy_ref_clk);
158
159 phy->aux_clk = devm_clk_get(dev, "pcie_aux");
160 if (IS_ERR(phy->aux_clk))
161 return PTR_ERR(phy->aux_clk);
162
163 phy->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy");
164 if (IS_ERR(phy->apb_phy_clk))
165 return PTR_ERR(phy->apb_phy_clk);
166
167 phy->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys");
168 if (IS_ERR(phy->apb_sys_clk))
169 return PTR_ERR(phy->apb_sys_clk);
170
171 phy->aclk = devm_clk_get(dev, "pcie_aclk");
172 if (IS_ERR(phy->aclk))
173 return PTR_ERR(phy->aclk);
174
175 return 0;
176}
177
178static int hi3660_pcie_phy_get_resource(struct hi3660_pcie_phy *phy)
179{
180 struct device *dev = phy->dev;
181 struct platform_device *pdev;
182
183 /* registers */
184 pdev = container_of(dev, struct platform_device, dev);
185
186 phy->base = devm_platform_ioremap_resource_byname(pdev, "phy");
187 if (IS_ERR(phy->base))
188 return PTR_ERR(phy->base);
189
190 phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
191 if (IS_ERR(phy->crgctrl))
192 return PTR_ERR(phy->crgctrl);
193
194 phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
195 if (IS_ERR(phy->sysctrl))
196 return PTR_ERR(phy->sysctrl);
197
Mauro Carvalho Chehab61d37542021-10-21 11:45:08 +0100198 return 0;
199}
200
201static int hi3660_pcie_phy_start(struct hi3660_pcie_phy *phy)
202{
203 struct device *dev = phy->dev;
204 u32 reg_val;
205
206 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1);
207 reg_val &= ~PHY_REF_PAD_BIT;
208 kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1);
209
210 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL0);
211 reg_val &= ~PHY_PWR_DOWN_BIT;
212 kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL0);
213 usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX);
214
215 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1);
216 reg_val &= ~PHY_RST_ACK_BIT;
217 kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1);
218
219 usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
220 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_STATUS0);
221 if (reg_val & PIPE_CLK_STABLE) {
222 dev_err(dev, "PIPE clk is not stable\n");
223 return -EINVAL;
224 }
225
226 return 0;
227}
228
229static void hi3660_pcie_phy_oe_enable(struct hi3660_pcie_phy *phy)
230{
231 u32 val;
232
233 regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
234 val |= PCIE_DEBOUNCE_PARAM;
235 val &= ~PCIE_OE_BYPASS;
236 regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
237}
238
239static int hi3660_pcie_phy_clk_ctrl(struct hi3660_pcie_phy *phy, bool enable)
240{
241 int ret = 0;
242
243 if (!enable)
244 goto close_clk;
245
246 ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ);
247 if (ret)
248 return ret;
249
250 ret = clk_prepare_enable(phy->phy_ref_clk);
251 if (ret)
252 return ret;
253
254 ret = clk_prepare_enable(phy->apb_sys_clk);
255 if (ret)
256 goto apb_sys_fail;
257
258 ret = clk_prepare_enable(phy->apb_phy_clk);
259 if (ret)
260 goto apb_phy_fail;
261
262 ret = clk_prepare_enable(phy->aclk);
263 if (ret)
264 goto aclk_fail;
265
266 ret = clk_prepare_enable(phy->aux_clk);
267 if (ret)
268 goto aux_clk_fail;
269
270 return 0;
271
272close_clk:
273 clk_disable_unprepare(phy->aux_clk);
274aux_clk_fail:
275 clk_disable_unprepare(phy->aclk);
276aclk_fail:
277 clk_disable_unprepare(phy->apb_phy_clk);
278apb_phy_fail:
279 clk_disable_unprepare(phy->apb_sys_clk);
280apb_sys_fail:
281 clk_disable_unprepare(phy->phy_ref_clk);
282
283 return ret;
284}
285
286static int hi3660_pcie_phy_power_on(struct kirin_pcie *pcie)
287{
288 struct hi3660_pcie_phy *phy = pcie->phy_priv;
289 int ret;
290
291 /* Power supply for Host */
292 regmap_write(phy->sysctrl,
293 SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
294 usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
295
296 hi3660_pcie_phy_oe_enable(phy);
297
298 ret = hi3660_pcie_phy_clk_ctrl(phy, true);
299 if (ret)
300 return ret;
301
302 /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
303 regmap_write(phy->sysctrl,
304 SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
305 regmap_write(phy->crgctrl,
306 CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
307 regmap_write(phy->sysctrl,
308 SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
309
310 ret = hi3660_pcie_phy_start(phy);
311 if (ret)
312 goto disable_clks;
313
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100314 return 0;
Mauro Carvalho Chehab61d37542021-10-21 11:45:08 +0100315
316disable_clks:
317 hi3660_pcie_phy_clk_ctrl(phy, false);
318 return ret;
319}
320
321static int hi3660_pcie_phy_init(struct platform_device *pdev,
322 struct kirin_pcie *pcie)
323{
324 struct device *dev = &pdev->dev;
325 struct hi3660_pcie_phy *phy;
326 int ret;
327
328 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
329 if (!phy)
330 return -ENOMEM;
331
332 pcie->phy_priv = phy;
333 phy->dev = dev;
334
335 /* registers */
336 pdev = container_of(dev, struct platform_device, dev);
337
338 ret = hi3660_pcie_phy_get_clk(phy);
339 if (ret)
340 return ret;
341
342 return hi3660_pcie_phy_get_resource(phy);
343}
344
Mauro Carvalho Chehab76afbdc2021-10-21 11:45:16 +0100345static int hi3660_pcie_phy_power_off(struct kirin_pcie *pcie)
346{
347 struct hi3660_pcie_phy *phy = pcie->phy_priv;
348
349 /* Drop power supply for Host */
350 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0x00);
351
352 hi3660_pcie_phy_clk_ctrl(phy, false);
353
354 return 0;
355}
356
Mauro Carvalho Chehab61d37542021-10-21 11:45:08 +0100357/*
358 * The non-PHY part starts here
359 */
360
Mauro Carvalho Chehabd19afe72021-10-21 11:45:10 +0100361static const struct regmap_config pcie_kirin_regmap_conf = {
362 .name = "kirin_pcie_apb",
363 .reg_bits = 32,
364 .val_bits = 32,
365 .reg_stride = 4,
366};
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800367
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100368static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie,
369 struct platform_device *pdev)
370{
371 struct device *dev = &pdev->dev;
372 struct device_node *np = dev->of_node;
373 char name[32];
374 int ret, i;
375
376 /* This is an optional property */
377 ret = of_gpio_named_count(np, "hisilicon,clken-gpios");
378 if (ret < 0)
379 return 0;
380
381 if (ret > MAX_PCI_SLOTS) {
382 dev_err(dev, "Too many GPIO clock requests!\n");
383 return -EINVAL;
384 }
385
386 pcie->n_gpio_clkreq = ret;
387
388 for (i = 0; i < pcie->n_gpio_clkreq; i++) {
389 pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node,
390 "hisilicon,clken-gpios", i);
391 if (pcie->gpio_id_clkreq[i] < 0)
392 return pcie->gpio_id_clkreq[i];
393
394 sprintf(name, "pcie_clkreq_%d", i);
395 pcie->clkreq_names[i] = devm_kstrdup_const(dev, name,
396 GFP_KERNEL);
397 if (!pcie->clkreq_names[i])
398 return -ENOMEM;
399 }
400
401 return 0;
402}
403
404static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
405 struct platform_device *pdev,
406 struct device_node *node)
407{
408 struct device *dev = &pdev->dev;
409 struct device_node *parent, *child;
410 int ret, slot, i;
411 char name[32];
412
413 for_each_available_child_of_node(node, parent) {
414 for_each_available_child_of_node(parent, child) {
415 i = pcie->num_slots;
416
417 pcie->gpio_id_reset[i] = of_get_named_gpio(child,
418 "reset-gpios", 0);
419 if (pcie->gpio_id_reset[i] < 0)
420 continue;
421
422 pcie->num_slots++;
423 if (pcie->num_slots > MAX_PCI_SLOTS) {
424 dev_err(dev, "Too many PCI slots!\n");
425 ret = -EINVAL;
426 goto put_node;
427 }
428
429 ret = of_pci_get_devfn(child);
430 if (ret < 0) {
431 dev_err(dev, "failed to parse devfn: %d\n", ret);
432 goto put_node;
433 }
434
435 slot = PCI_SLOT(ret);
436
437 sprintf(name, "pcie_perst_%d", slot);
438 pcie->reset_names[i] = devm_kstrdup_const(dev, name,
439 GFP_KERNEL);
440 if (!pcie->reset_names[i]) {
441 ret = -ENOMEM;
442 goto put_node;
443 }
444 }
445 }
446
447 return 0;
448
449put_node:
450 of_node_put(child);
451 of_node_put(parent);
452 return ret;
453}
454
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800455static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
456 struct platform_device *pdev)
457{
Mauro Carvalho Chehabd19afe72021-10-21 11:45:10 +0100458 struct device *dev = &pdev->dev;
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100459 struct device_node *child, *node = dev->of_node;
Mauro Carvalho Chehabd19afe72021-10-21 11:45:10 +0100460 void __iomem *apb_base;
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100461 int ret;
Mauro Carvalho Chehabd19afe72021-10-21 11:45:10 +0100462
463 apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
464 if (IS_ERR(apb_base))
465 return PTR_ERR(apb_base);
466
467 kirin_pcie->apb = devm_regmap_init_mmio(dev, apb_base,
468 &pcie_kirin_regmap_conf);
469 if (IS_ERR(kirin_pcie->apb))
470 return PTR_ERR(kirin_pcie->apb);
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800471
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100472 /* pcie internal PERST# gpio */
473 kirin_pcie->gpio_id_dwc_perst = of_get_named_gpio(dev->of_node,
474 "reset-gpios", 0);
475 if (kirin_pcie->gpio_id_dwc_perst == -EPROBE_DEFER) {
476 return -EPROBE_DEFER;
477 } else if (!gpio_is_valid(kirin_pcie->gpio_id_dwc_perst)) {
478 dev_err(dev, "unable to get a valid gpio pin\n");
479 return -ENODEV;
480 }
481
482 ret = kirin_pcie_get_gpio_enable(kirin_pcie, pdev);
483 if (ret)
484 return ret;
485
486 /* Parse OF children */
487 for_each_available_child_of_node(node, child) {
488 ret = kirin_pcie_parse_port(kirin_pcie, pdev, child);
489 if (ret)
490 goto put_node;
491 }
492
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800493 return 0;
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100494
495put_node:
496 of_node_put(child);
497 return ret;
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800498}
499
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800500static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
501 bool on)
502{
503 u32 val;
504
Mauro Carvalho Chehabd19afe72021-10-21 11:45:10 +0100505 regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, &val);
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800506 if (on)
507 val = val | PCIE_ELBI_SLV_DBI_ENABLE;
508 else
509 val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
510
Mauro Carvalho Chehabd19afe72021-10-21 11:45:10 +0100511 regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, val);
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800512}
513
514static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
515 bool on)
516{
517 u32 val;
518
Mauro Carvalho Chehabd19afe72021-10-21 11:45:10 +0100519 regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, &val);
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800520 if (on)
521 val = val | PCIE_ELBI_SLV_DBI_ENABLE;
522 else
523 val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
524
Mauro Carvalho Chehabd19afe72021-10-21 11:45:10 +0100525 regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, val);
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800526}
527
Rob Herring6408e6a2020-08-20 21:53:49 -0600528static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800529 int where, int size, u32 *val)
530{
Rob Herring6408e6a2020-08-20 21:53:49 -0600531 struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800532
Rob Herring6408e6a2020-08-20 21:53:49 -0600533 if (PCI_SLOT(devfn)) {
534 *val = ~0;
535 return PCIBIOS_DEVICE_NOT_FOUND;
536 }
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800537
Rob Herring6408e6a2020-08-20 21:53:49 -0600538 *val = dw_pcie_read_dbi(pci, where, size);
539 return PCIBIOS_SUCCESSFUL;
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800540}
541
Rob Herring6408e6a2020-08-20 21:53:49 -0600542static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn,
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800543 int where, int size, u32 val)
544{
Rob Herring6408e6a2020-08-20 21:53:49 -0600545 struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800546
Rob Herring6408e6a2020-08-20 21:53:49 -0600547 if (PCI_SLOT(devfn))
548 return PCIBIOS_DEVICE_NOT_FOUND;
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800549
Rob Herring6408e6a2020-08-20 21:53:49 -0600550 dw_pcie_write_dbi(pci, where, size, val);
551 return PCIBIOS_SUCCESSFUL;
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800552}
553
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100554static int kirin_pcie_add_bus(struct pci_bus *bus)
555{
556 struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
557 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
558 int i, ret;
559
560 if (!kirin_pcie->num_slots)
561 return 0;
562
563 /* Send PERST# to each slot */
564 for (i = 0; i < kirin_pcie->num_slots; i++) {
565 ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1);
566 if (ret) {
567 dev_err(pci->dev, "PERST# %s error: %d\n",
568 kirin_pcie->reset_names[i], ret);
569 }
570 }
571 usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
572
573 return 0;
574}
575
Rob Herring6408e6a2020-08-20 21:53:49 -0600576static struct pci_ops kirin_pci_ops = {
577 .read = kirin_pcie_rd_own_conf,
578 .write = kirin_pcie_wr_own_conf,
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100579 .add_bus = kirin_pcie_add_bus,
Rob Herring6408e6a2020-08-20 21:53:49 -0600580};
581
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800582static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
583 u32 reg, size_t size)
584{
585 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
586 u32 ret;
587
588 kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
589 dw_pcie_read(base + reg, size, &ret);
590 kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
591
592 return ret;
593}
594
595static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
596 u32 reg, size_t size, u32 val)
597{
598 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
599
600 kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
601 dw_pcie_write(base + reg, size, val);
602 kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
603}
604
605static int kirin_pcie_link_up(struct dw_pcie *pci)
606{
607 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
Mauro Carvalho Chehabd19afe72021-10-21 11:45:10 +0100608 u32 val;
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800609
Mauro Carvalho Chehabd19afe72021-10-21 11:45:10 +0100610 regmap_read(kirin_pcie->apb, PCIE_APB_PHY_STATUS0, &val);
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800611 if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
612 return 1;
613
614 return 0;
615}
616
Rob Herring886a9c12020-11-05 15:11:53 -0600617static int kirin_pcie_start_link(struct dw_pcie *pci)
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800618{
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800619 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800620
621 /* assert LTSSM enable */
Mauro Carvalho Chehabd19afe72021-10-21 11:45:10 +0100622 regmap_write(kirin_pcie->apb, PCIE_APP_LTSSM_ENABLE,
623 PCIE_LTSSM_ENABLE_BIT);
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800624
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800625 return 0;
626}
627
Bjorn Andersson4a301762017-07-15 23:39:45 -0700628static int kirin_pcie_host_init(struct pcie_port *pp)
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800629{
Rob Herring6408e6a2020-08-20 21:53:49 -0600630 pp->bridge->ops = &kirin_pci_ops;
631
Bjorn Andersson4a301762017-07-15 23:39:45 -0700632 return 0;
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800633}
634
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100635static int kirin_pcie_gpio_request(struct kirin_pcie *kirin_pcie,
636 struct device *dev)
637{
638 int ret, i;
639
640 for (i = 0; i < kirin_pcie->num_slots; i++) {
641 if (!gpio_is_valid(kirin_pcie->gpio_id_reset[i])) {
642 dev_err(dev, "unable to get a valid %s gpio\n",
643 kirin_pcie->reset_names[i]);
644 return -ENODEV;
645 }
646
647 ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i],
648 kirin_pcie->reset_names[i]);
649 if (ret)
650 return ret;
651 }
652
653 for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) {
654 if (!gpio_is_valid(kirin_pcie->gpio_id_clkreq[i])) {
655 dev_err(dev, "unable to get a valid %s gpio\n",
656 kirin_pcie->clkreq_names[i]);
657 return -ENODEV;
658 }
659
660 ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i],
661 kirin_pcie->clkreq_names[i]);
662 if (ret)
663 return ret;
664
665 ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0);
666 if (ret)
667 return ret;
668 }
669
670 return 0;
671}
672
Nishka Dasgupta5ae63932019-08-19 13:09:46 +0530673static const struct dw_pcie_ops kirin_dw_pcie_ops = {
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800674 .read_dbi = kirin_pcie_read_dbi,
675 .write_dbi = kirin_pcie_write_dbi,
676 .link_up = kirin_pcie_link_up,
Rob Herring886a9c12020-11-05 15:11:53 -0600677 .start_link = kirin_pcie_start_link,
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800678};
679
Bhumika Goyaldb2af312017-08-09 13:18:48 +0530680static const struct dw_pcie_host_ops kirin_pcie_host_ops = {
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800681 .host_init = kirin_pcie_host_init,
682};
683
Mauro Carvalho Chehab79cf0142021-10-21 11:45:17 +0100684static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie)
685{
686 int i;
687
688 if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY)
689 return hi3660_pcie_phy_power_off(kirin_pcie);
690
691 phy_power_off(kirin_pcie->phy);
692 phy_exit(kirin_pcie->phy);
693
694 return 0;
695}
696
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100697static int kirin_pcie_power_on(struct platform_device *pdev,
698 struct kirin_pcie *kirin_pcie)
699{
700 struct device *dev = &pdev->dev;
701 int ret;
702
703 if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) {
704 ret = hi3660_pcie_phy_init(pdev, kirin_pcie);
705 if (ret)
706 return ret;
707
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100708 ret = hi3660_pcie_phy_power_on(kirin_pcie);
709 if (ret)
710 return ret;
711 } else {
712 kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL);
713 if (IS_ERR(kirin_pcie->phy))
714 return PTR_ERR(kirin_pcie->phy);
715
716 ret = kirin_pcie_gpio_request(kirin_pcie, dev);
717 if (ret)
718 return ret;
719
720 ret = phy_init(kirin_pcie->phy);
721 if (ret)
722 goto err;
723
724 ret = phy_power_on(kirin_pcie->phy);
725 if (ret)
726 goto err;
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100727 }
728
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100729 /* perst assert Endpoint */
730 usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100731
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100732 if (!gpio_request(kirin_pcie->gpio_id_dwc_perst, "pcie_perst_bridge")) {
733 ret = gpio_direction_output(kirin_pcie->gpio_id_dwc_perst, 1);
734 if (ret)
735 goto err;
736 }
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100737
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100738 usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100739
740 return 0;
741err:
Mauro Carvalho Chehab79cf0142021-10-21 11:45:17 +0100742 kirin_pcie_power_off(kirin_pcie);
Mauro Carvalho Chehabb22dbbb2021-10-21 11:45:11 +0100743
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100744 return ret;
745}
746
747static int __exit kirin_pcie_remove(struct platform_device *pdev)
748{
749 struct kirin_pcie *kirin_pcie = platform_get_drvdata(pdev);
750
Mauro Carvalho Chehab79cf0142021-10-21 11:45:17 +0100751 kirin_pcie_power_off(kirin_pcie);
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100752
753 return 0;
754}
755
756static const struct of_device_id kirin_pcie_match[] = {
757 {
758 .compatible = "hisilicon,kirin960-pcie",
759 .data = (void *)PCIE_KIRIN_INTERNAL_PHY
760 },
Mauro Carvalho Chehabe636c162021-10-21 11:45:13 +0100761 {
762 .compatible = "hisilicon,kirin970-pcie",
763 .data = (void *)PCIE_KIRIN_EXTERNAL_PHY
764 },
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100765 {},
766};
767
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800768static int kirin_pcie_probe(struct platform_device *pdev)
769{
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100770 enum pcie_kirin_phy_type phy_type;
771 const struct of_device_id *of_id;
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800772 struct device *dev = &pdev->dev;
773 struct kirin_pcie *kirin_pcie;
774 struct dw_pcie *pci;
775 int ret;
776
777 if (!dev->of_node) {
778 dev_err(dev, "NULL node\n");
779 return -EINVAL;
780 }
781
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100782 of_id = of_match_device(kirin_pcie_match, dev);
783 if (!of_id) {
784 dev_err(dev, "OF data missing\n");
785 return -EINVAL;
786 }
787
788 phy_type = (long)of_id->data;
789
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800790 kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL);
791 if (!kirin_pcie)
792 return -ENOMEM;
793
794 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
795 if (!pci)
796 return -ENOMEM;
797
798 pci->dev = dev;
799 pci->ops = &kirin_dw_pcie_ops;
Rob Herring60f5b732020-11-05 15:11:56 -0600800 pci->pp.ops = &kirin_pcie_host_ops;
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800801 kirin_pcie->pci = pci;
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100802 kirin_pcie->type = phy_type;
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800803
804 ret = kirin_pcie_get_resource(kirin_pcie, pdev);
805 if (ret)
806 return ret;
807
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100808 platform_set_drvdata(pdev, kirin_pcie);
809
810 ret = kirin_pcie_power_on(pdev, kirin_pcie);
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800811 if (ret)
812 return ret;
813
Rob Herring60f5b732020-11-05 15:11:56 -0600814 return dw_pcie_host_init(&pci->pp);
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800815}
816
Fengguang Wue7340162018-03-20 17:12:12 +0000817static struct platform_driver kirin_pcie_driver = {
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800818 .probe = kirin_pcie_probe,
Mauro Carvalho Chehab000f60d2021-10-21 11:45:09 +0100819 .remove = __exit_p(kirin_pcie_remove),
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800820 .driver = {
821 .name = "kirin-pcie",
Mauro Carvalho Chehab61d37542021-10-21 11:45:08 +0100822 .of_match_table = kirin_pcie_match,
823 .suppress_bind_attrs = true,
Xiaowei Songfc5165d2017-06-19 18:23:48 +0800824 },
825};
826builtin_platform_driver(kirin_pcie_driver);
Mauro Carvalho Chehaba4099c592021-10-21 11:45:14 +0100827
828MODULE_DEVICE_TABLE(of, kirin_pcie_match);
829MODULE_DESCRIPTION("PCIe host controller driver for Kirin Phone SoCs");
830MODULE_AUTHOR("Xiaowei Song <songxiaowei@huawei.com>");
831MODULE_LICENSE("GPL v2");