| Andres Salomon | 2272b0e | 2007-03-06 01:42:05 -0800 | [diff] [blame] | 1 | /* |
| Thomas Gleixner | 2f0798a | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 2 | * x86 TSC related functions |
| Andres Salomon | 2272b0e | 2007-03-06 01:42:05 -0800 | [diff] [blame] | 3 | */ |
| H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 4 | #ifndef _ASM_X86_TSC_H |
| 5 | #define _ASM_X86_TSC_H |
| Andres Salomon | 2272b0e | 2007-03-06 01:42:05 -0800 | [diff] [blame] | 6 | |
| 7 | #include <asm/processor.h> |
| 8 | |
| Thomas Gleixner | 2f0798a | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 9 | #define NS_SCALE 10 /* 2^10, carefully chosen */ |
| 10 | #define US_SCALE 32 /* 2^32, arbitralrily chosen */ |
| 11 | |
| Andres Salomon | 2272b0e | 2007-03-06 01:42:05 -0800 | [diff] [blame] | 12 | /* |
| 13 | * Standard way to access the cycle counter. |
| 14 | */ |
| 15 | typedef unsigned long long cycles_t; |
| 16 | |
| 17 | extern unsigned int cpu_khz; |
| 18 | extern unsigned int tsc_khz; |
| Glauber de Oliveira Costa | 73018a6 | 2008-01-30 13:31:26 +0100 | [diff] [blame] | 19 | |
| 20 | extern void disable_TSC(void); |
| Andres Salomon | 2272b0e | 2007-03-06 01:42:05 -0800 | [diff] [blame] | 21 | |
| 22 | static inline cycles_t get_cycles(void) |
| 23 | { |
| Andres Salomon | 2272b0e | 2007-03-06 01:42:05 -0800 | [diff] [blame] | 24 | #ifndef CONFIG_X86_TSC |
| 25 | if (!cpu_has_tsc) |
| 26 | return 0; |
| 27 | #endif |
| Ingo Molnar | 75f2ce0 | 2008-01-30 13:33:24 +0100 | [diff] [blame] | 28 | |
| Andy Lutomirski | 87be28a | 2015-06-25 18:43:58 +0200 | [diff] [blame] | 29 | return native_read_tsc(); |
| Andres Salomon | 2272b0e | 2007-03-06 01:42:05 -0800 | [diff] [blame] | 30 | } |
| 31 | |
| Andres Salomon | 2272b0e | 2007-03-06 01:42:05 -0800 | [diff] [blame] | 32 | extern void tsc_init(void); |
| john stultz | 5a90cf2 | 2007-05-02 19:27:08 +0200 | [diff] [blame] | 33 | extern void mark_tsc_unstable(char *reason); |
| Andres Salomon | 2272b0e | 2007-03-06 01:42:05 -0800 | [diff] [blame] | 34 | extern int unsynchronized_tsc(void); |
| Thomas Gleixner | 2d82640 | 2009-08-20 17:06:25 +0200 | [diff] [blame] | 35 | extern int check_tsc_unstable(void); |
| Adrian Hunter | c73deb6 | 2013-06-28 16:22:18 +0300 | [diff] [blame] | 36 | extern int check_tsc_disabled(void); |
| Thomas Gleixner | 2d82640 | 2009-08-20 17:06:25 +0200 | [diff] [blame] | 37 | extern unsigned long native_calibrate_tsc(void); |
| Andres Salomon | 2272b0e | 2007-03-06 01:42:05 -0800 | [diff] [blame] | 38 | |
| Suresh Siddha | 28a0018 | 2011-11-04 15:42:17 -0700 | [diff] [blame] | 39 | extern int tsc_clocksource_reliable; |
| 40 | |
| Andres Salomon | 2272b0e | 2007-03-06 01:42:05 -0800 | [diff] [blame] | 41 | /* |
| 42 | * Boot-time check whether the TSCs are synchronized across |
| 43 | * all CPUs/cores: |
| 44 | */ |
| 45 | extern void check_tsc_sync_source(int cpu); |
| 46 | extern void check_tsc_sync_target(void); |
| 47 | |
| Thomas Gleixner | 80ca9c9 | 2008-01-30 13:30:18 +0100 | [diff] [blame] | 48 | extern int notsc_setup(char *); |
| Marcelo Tosatti | b74f05d6 | 2012-02-13 11:07:27 -0200 | [diff] [blame] | 49 | extern void tsc_save_sched_clock_state(void); |
| 50 | extern void tsc_restore_sched_clock_state(void); |
| Thomas Gleixner | d371698 | 2007-10-12 23:04:06 +0200 | [diff] [blame] | 51 | |
| Bin Gao | 7da7c15 | 2013-10-21 09:16:33 -0700 | [diff] [blame] | 52 | /* MSR based TSC calibration for Intel Atom SoC platforms */ |
| Thomas Gleixner | 5f0e030 | 2014-02-19 13:52:29 +0200 | [diff] [blame] | 53 | unsigned long try_msr_calibrate_tsc(void); |
| Bin Gao | 7da7c15 | 2013-10-21 09:16:33 -0700 | [diff] [blame] | 54 | |
| H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 55 | #endif /* _ASM_X86_TSC_H */ |