blob: 0d9c36e1e806c0336b8c9b5e3fb3d9d7dd382ae0 [file] [log] [blame]
Alex Elder1ed7d0c02020-03-05 22:28:18 -06001// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2020 Linaro Ltd.
5 */
6
7#include <linux/log2.h>
8
9#include "gsi.h"
10#include "ipa_data.h"
11#include "ipa_endpoint.h"
12#include "ipa_mem.h"
13
14/* Endpoint configuration for the SDM845 SoC. */
15static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
16 [IPA_ENDPOINT_AP_COMMAND_TX] = {
17 .ee_id = GSI_EE_AP,
18 .channel_id = 4,
19 .endpoint_id = 5,
20 .toward_ipa = true,
21 .channel = {
22 .tre_count = 512,
23 .event_count = 256,
24 .tlv_count = 20,
25 },
26 .endpoint = {
27 .seq_type = IPA_SEQ_DMA_ONLY,
28 .config = {
29 .dma_mode = true,
30 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
31 },
32 },
33 },
34 [IPA_ENDPOINT_AP_LAN_RX] = {
35 .ee_id = GSI_EE_AP,
36 .channel_id = 5,
37 .endpoint_id = 9,
38 .toward_ipa = false,
39 .channel = {
40 .tre_count = 256,
41 .event_count = 256,
42 .tlv_count = 8,
43 },
44 .endpoint = {
45 .seq_type = IPA_SEQ_INVALID,
46 .config = {
47 .checksum = true,
48 .aggregation = true,
49 .status_enable = true,
50 .rx = {
51 .pad_align = ilog2(sizeof(u32)),
52 },
53 },
54 },
55 },
56 [IPA_ENDPOINT_AP_MODEM_TX] = {
57 .ee_id = GSI_EE_AP,
58 .channel_id = 3,
59 .endpoint_id = 2,
60 .toward_ipa = true,
61 .channel = {
62 .tre_count = 512,
63 .event_count = 512,
64 .tlv_count = 16,
65 },
66 .endpoint = {
67 .filter_support = true,
68 .seq_type =
69 IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
70 .config = {
71 .checksum = true,
72 .qmap = true,
73 .status_enable = true,
74 .tx = {
75 .status_endpoint =
76 IPA_ENDPOINT_MODEM_AP_RX,
77 .delay = true,
78 },
79 },
80 },
81 },
82 [IPA_ENDPOINT_AP_MODEM_RX] = {
83 .ee_id = GSI_EE_AP,
84 .channel_id = 6,
85 .endpoint_id = 10,
86 .toward_ipa = false,
87 .channel = {
88 .tre_count = 256,
89 .event_count = 256,
90 .tlv_count = 8,
91 },
92 .endpoint = {
93 .seq_type = IPA_SEQ_INVALID,
94 .config = {
95 .checksum = true,
96 .qmap = true,
97 .aggregation = true,
98 .rx = {
99 .aggr_close_eof = true,
100 },
101 },
102 },
103 },
104 [IPA_ENDPOINT_MODEM_COMMAND_TX] = {
105 .ee_id = GSI_EE_MODEM,
106 .channel_id = 1,
107 .endpoint_id = 4,
108 .toward_ipa = true,
109 },
110 [IPA_ENDPOINT_MODEM_LAN_TX] = {
111 .ee_id = GSI_EE_MODEM,
112 .channel_id = 0,
113 .endpoint_id = 3,
114 .toward_ipa = true,
115 .endpoint = {
116 .filter_support = true,
117 },
118 },
119 [IPA_ENDPOINT_MODEM_LAN_RX] = {
120 .ee_id = GSI_EE_MODEM,
121 .channel_id = 3,
122 .endpoint_id = 13,
123 .toward_ipa = false,
124 },
125 [IPA_ENDPOINT_MODEM_AP_TX] = {
126 .ee_id = GSI_EE_MODEM,
127 .channel_id = 4,
128 .endpoint_id = 6,
129 .toward_ipa = true,
130 .endpoint = {
131 .filter_support = true,
132 },
133 },
134 [IPA_ENDPOINT_MODEM_AP_RX] = {
135 .ee_id = GSI_EE_MODEM,
136 .channel_id = 2,
137 .endpoint_id = 12,
138 .toward_ipa = false,
139 },
140};
141
142/* For the SDM845, resource groups are allocated this way:
143 * group 0: LWA_DL
144 * group 1: UL_DL
145 */
146static const struct ipa_resource_src ipa_resource_src[] = {
147 {
148 .type = IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS,
149 .limits[0] = {
150 .min = 1,
151 .max = 63,
152 },
153 .limits[1] = {
154 .min = 1,
155 .max = 63,
156 },
157 },
158 {
159 .type = IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
160 .limits[0] = {
161 .min = 10,
162 .max = 10,
163 },
164 .limits[1] = {
165 .min = 10,
166 .max = 10,
167 },
168 },
169 {
170 .type = IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
171 .limits[0] = {
172 .min = 12,
173 .max = 12,
174 },
175 .limits[1] = {
176 .min = 14,
177 .max = 14,
178 },
179 },
180 {
181 .type = IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
182 .limits[0] = {
183 .min = 0,
184 .max = 63,
185 },
186 .limits[1] = {
187 .min = 0,
188 .max = 63,
189 },
190 },
191 {
192 .type = IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
193 .limits[0] = {
194 .min = 14,
195 .max = 14,
196 },
197 .limits[1] = {
198 .min = 20,
199 .max = 20,
200 },
201 },
202};
203
204static const struct ipa_resource_dst ipa_resource_dst[] = {
205 {
206 .type = IPA_RESOURCE_TYPE_DST_DATA_SECTORS,
207 .limits[0] = {
208 .min = 4,
209 .max = 4,
210 },
211 .limits[1] = {
212 .min = 4,
213 .max = 4,
214 },
215 },
216 {
217 .type = IPA_RESOURCE_TYPE_DST_DPS_DMARS,
218 .limits[0] = {
219 .min = 2,
220 .max = 63,
221 },
222 .limits[1] = {
223 .min = 1,
224 .max = 63,
225 },
226 },
227};
228
229/* Resource configuration for the SDM845 SoC. */
230static const struct ipa_resource_data ipa_resource_data = {
231 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
232 .resource_src = ipa_resource_src,
233 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
234 .resource_dst = ipa_resource_dst,
235};
236
237/* IPA-resident memory region configuration for the SDM845 SoC. */
238static const struct ipa_mem ipa_mem_data[] = {
239 [IPA_MEM_UC_SHARED] = {
240 .offset = 0x0000,
241 .size = 0x0080,
242 .canary_count = 0,
243 },
244 [IPA_MEM_UC_INFO] = {
245 .offset = 0x0080,
246 .size = 0x0200,
247 .canary_count = 0,
248 },
249 [IPA_MEM_V4_FILTER_HASHED] = {
250 .offset = 0x0288,
251 .size = 0x0078,
252 .canary_count = 2,
253 },
254 [IPA_MEM_V4_FILTER] = {
255 .offset = 0x0308,
256 .size = 0x0078,
257 .canary_count = 2,
258 },
259 [IPA_MEM_V6_FILTER_HASHED] = {
260 .offset = 0x0388,
261 .size = 0x0078,
262 .canary_count = 2,
263 },
264 [IPA_MEM_V6_FILTER] = {
265 .offset = 0x0408,
266 .size = 0x0078,
267 .canary_count = 2,
268 },
269 [IPA_MEM_V4_ROUTE_HASHED] = {
270 .offset = 0x0488,
271 .size = 0x0078,
272 .canary_count = 2,
273 },
274 [IPA_MEM_V4_ROUTE] = {
275 .offset = 0x0508,
276 .size = 0x0078,
277 .canary_count = 2,
278 },
279 [IPA_MEM_V6_ROUTE_HASHED] = {
280 .offset = 0x0588,
281 .size = 0x0078,
282 .canary_count = 2,
283 },
284 [IPA_MEM_V6_ROUTE] = {
285 .offset = 0x0608,
286 .size = 0x0078,
287 .canary_count = 2,
288 },
289 [IPA_MEM_MODEM_HEADER] = {
290 .offset = 0x0688,
291 .size = 0x0140,
292 .canary_count = 2,
293 },
294 [IPA_MEM_AP_HEADER] = {
295 .offset = 0x07c8,
296 .size = 0x0000,
297 .canary_count = 0,
298 },
299 [IPA_MEM_MODEM_PROC_CTX] = {
300 .offset = 0x07d0,
301 .size = 0x0200,
302 .canary_count = 2,
303 },
304 [IPA_MEM_AP_PROC_CTX] = {
305 .offset = 0x09d0,
306 .size = 0x0200,
307 .canary_count = 0,
308 },
309 [IPA_MEM_MODEM] = {
310 .offset = 0x0bd8,
311 .size = 0x1024,
312 .canary_count = 0,
313 },
314 [IPA_MEM_UC_EVENT_RING] = {
315 .offset = 0x1c00,
316 .size = 0x0400,
317 .canary_count = 1,
318 },
319};
320
321/* Configuration data for the SDM845 SoC. */
322const struct ipa_data ipa_data_sdm845 = {
323 .version = IPA_VERSION_3_5_1,
324 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
325 .endpoint_data = ipa_gsi_endpoint_data,
326 .resource_data = &ipa_resource_data,
327 .mem_count = ARRAY_SIZE(ipa_mem_data),
328 .mem_data = ipa_mem_data,
329};