Sean Wang | a1a503a | 2018-09-08 19:07:17 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2018 MediaTek Inc. |
| 4 | * |
| 5 | * Author: Sean Wang <sean.wang@mediatek.com> |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | #ifndef __PINCTRL_MTK_COMMON_V2_H |
| 10 | #define __PINCTRL_MTK_COMMON_V2_H |
| 11 | |
Sean Wang | a1a503a | 2018-09-08 19:07:17 +0800 | [diff] [blame] | 12 | #define MTK_INPUT 0 |
| 13 | #define MTK_OUTPUT 1 |
| 14 | #define MTK_DISABLE 0 |
| 15 | #define MTK_ENABLE 1 |
| 16 | |
Sean Wang | fb5fa8d | 2018-09-08 19:07:20 +0800 | [diff] [blame] | 17 | #define EINT_NA -1 |
| 18 | |
Sean Wang | b906faf | 2018-09-08 19:07:19 +0800 | [diff] [blame] | 19 | #define PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ |
| 20 | _x_bits, _sz_reg, _fixed) { \ |
| 21 | .s_pin = _s_pin, \ |
| 22 | .e_pin = _e_pin, \ |
| 23 | .s_addr = _s_addr, \ |
| 24 | .x_addrs = _x_addrs, \ |
| 25 | .s_bit = _s_bit, \ |
| 26 | .x_bits = _x_bits, \ |
| 27 | .sz_reg = _sz_reg, \ |
| 28 | .fixed = _fixed, \ |
| 29 | } |
| 30 | |
| 31 | #define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ |
| 32 | PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ |
| 33 | _x_bits, 32, 0) |
| 34 | |
| 35 | #define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ |
| 36 | PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ |
| 37 | _x_bits, 32, 1) |
| 38 | |
Sean Wang | a1a503a | 2018-09-08 19:07:17 +0800 | [diff] [blame] | 39 | /* List these attributes which could be modified for the pin */ |
| 40 | enum { |
| 41 | PINCTRL_PIN_REG_MODE, |
| 42 | PINCTRL_PIN_REG_DIR, |
| 43 | PINCTRL_PIN_REG_DI, |
| 44 | PINCTRL_PIN_REG_DO, |
| 45 | PINCTRL_PIN_REG_SR, |
| 46 | PINCTRL_PIN_REG_SMT, |
| 47 | PINCTRL_PIN_REG_PD, |
| 48 | PINCTRL_PIN_REG_PU, |
| 49 | PINCTRL_PIN_REG_E4, |
| 50 | PINCTRL_PIN_REG_E8, |
| 51 | PINCTRL_PIN_REG_TDSEL, |
| 52 | PINCTRL_PIN_REG_RDSEL, |
Sean Wang | c283219 | 2018-09-08 19:07:22 +0800 | [diff] [blame] | 53 | PINCTRL_PIN_REG_DRV, |
Sean Wang | 0d7ca77 | 2018-09-08 19:07:25 +0800 | [diff] [blame^] | 54 | PINCTRL_PIN_REG_PUPD, |
| 55 | PINCTRL_PIN_REG_R0, |
| 56 | PINCTRL_PIN_REG_R1, |
Sean Wang | a1a503a | 2018-09-08 19:07:17 +0800 | [diff] [blame] | 57 | PINCTRL_PIN_REG_MAX, |
| 58 | }; |
| 59 | |
Sean Wang | fb5fa8d | 2018-09-08 19:07:20 +0800 | [diff] [blame] | 60 | /* Group the pins by the driving current */ |
| 61 | enum { |
| 62 | DRV_FIXED, |
| 63 | DRV_GRP0, |
| 64 | DRV_GRP1, |
| 65 | DRV_GRP2, |
| 66 | DRV_GRP3, |
| 67 | DRV_GRP4, |
| 68 | DRV_GRP_MAX, |
| 69 | }; |
| 70 | |
Sean Wang | a1a503a | 2018-09-08 19:07:17 +0800 | [diff] [blame] | 71 | /* struct mtk_pin_field - the structure that holds the information of the field |
| 72 | * used to describe the attribute for the pin |
| 73 | * @offset: the register offset relative to the base address |
| 74 | * @mask: the mask used to filter out the field from the register |
| 75 | * @bitpos: the start bit relative to the register |
| 76 | * @next: the indication that the field would be extended to the |
| 77 | next register |
| 78 | */ |
| 79 | struct mtk_pin_field { |
| 80 | u32 offset; |
| 81 | u32 mask; |
| 82 | u8 bitpos; |
| 83 | u8 next; |
| 84 | }; |
| 85 | |
| 86 | /* struct mtk_pin_field_calc - the structure that holds the range providing |
| 87 | * the guide used to look up the relevant field |
| 88 | * @s_pin: the start pin within the range |
| 89 | * @e_pin: the end pin within the range |
| 90 | * @s_addr: the start address for the range |
| 91 | * @x_addrs: the address distance between two consecutive registers |
| 92 | * within the range |
| 93 | * @s_bit: the start bit for the first register within the range |
| 94 | * @x_bits: the bit distance between two consecutive pins within |
| 95 | * the range |
Sean Wang | b906faf | 2018-09-08 19:07:19 +0800 | [diff] [blame] | 96 | * @sz_reg: the size of bits in a register |
| 97 | * @fixed: the consecutive pins share the same bits with the 1st |
| 98 | * pin |
Sean Wang | a1a503a | 2018-09-08 19:07:17 +0800 | [diff] [blame] | 99 | */ |
| 100 | struct mtk_pin_field_calc { |
| 101 | u16 s_pin; |
| 102 | u16 e_pin; |
| 103 | u32 s_addr; |
| 104 | u8 x_addrs; |
| 105 | u8 s_bit; |
| 106 | u8 x_bits; |
Sean Wang | b906faf | 2018-09-08 19:07:19 +0800 | [diff] [blame] | 107 | u8 sz_reg; |
| 108 | u8 fixed; |
Sean Wang | a1a503a | 2018-09-08 19:07:17 +0800 | [diff] [blame] | 109 | }; |
| 110 | |
| 111 | /* struct mtk_pin_reg_calc - the structure that holds all ranges used to |
| 112 | * determine which register the pin would make use of |
| 113 | * for certain pin attribute. |
| 114 | * @range: the start address for the range |
| 115 | * @nranges: the number of items in the range |
| 116 | */ |
| 117 | struct mtk_pin_reg_calc { |
| 118 | const struct mtk_pin_field_calc *range; |
| 119 | unsigned int nranges; |
| 120 | }; |
| 121 | |
Sean Wang | fb5fa8d | 2018-09-08 19:07:20 +0800 | [diff] [blame] | 122 | /** |
| 123 | * struct mtk_pin_desc - the structure that providing information |
| 124 | * for each pin of chips |
| 125 | * @number: unique pin number from the global pin number space |
| 126 | * @name: name for this pin |
| 127 | * @eint_n: the eint number for this pin |
| 128 | * @drv_n: the index with the driving group |
| 129 | */ |
| 130 | struct mtk_pin_desc { |
| 131 | unsigned int number; |
| 132 | const char *name; |
| 133 | u16 eint_n; |
| 134 | u8 drv_n; |
| 135 | }; |
| 136 | |
Sean Wang | c283219 | 2018-09-08 19:07:22 +0800 | [diff] [blame] | 137 | struct mtk_pinctrl; |
| 138 | |
Sean Wang | a1a503a | 2018-09-08 19:07:17 +0800 | [diff] [blame] | 139 | /* struct mtk_pin_soc - the structure that holds SoC-specific data */ |
| 140 | struct mtk_pin_soc { |
| 141 | const struct mtk_pin_reg_calc *reg_cal; |
| 142 | const struct pinctrl_pin_desc *pins; |
| 143 | unsigned int npins; |
| 144 | const struct group_desc *grps; |
| 145 | unsigned int ngrps; |
| 146 | const struct function_desc *funcs; |
| 147 | unsigned int nfuncs; |
| 148 | const struct mtk_eint_regs *eint_regs; |
| 149 | const struct mtk_eint_hw *eint_hw; |
Sean Wang | 1dc5e53 | 2018-09-08 19:07:21 +0800 | [diff] [blame] | 150 | |
| 151 | /* Specific parameters per SoC */ |
| 152 | u8 gpio_m; |
| 153 | u8 eint_m; |
Sean Wang | c283219 | 2018-09-08 19:07:22 +0800 | [diff] [blame] | 154 | |
| 155 | /* Specific pinconfig operations */ |
Sean Wang | 85430152 | 2018-09-08 19:07:24 +0800 | [diff] [blame] | 156 | int (*bias_disable_set)(struct mtk_pinctrl *hw, |
| 157 | const struct mtk_pin_desc *desc); |
| 158 | int (*bias_disable_get)(struct mtk_pinctrl *hw, |
| 159 | const struct mtk_pin_desc *desc, int *res); |
| 160 | int (*bias_set)(struct mtk_pinctrl *hw, |
| 161 | const struct mtk_pin_desc *desc, bool pullup); |
| 162 | int (*bias_get)(struct mtk_pinctrl *hw, |
| 163 | const struct mtk_pin_desc *desc, bool pullup, int *res); |
| 164 | |
Sean Wang | c283219 | 2018-09-08 19:07:22 +0800 | [diff] [blame] | 165 | int (*drive_set)(struct mtk_pinctrl *hw, |
| 166 | const struct mtk_pin_desc *desc, u32 arg); |
| 167 | int (*drive_get)(struct mtk_pinctrl *hw, |
| 168 | const struct mtk_pin_desc *desc, int *val); |
Sean Wang | 0d7ca77 | 2018-09-08 19:07:25 +0800 | [diff] [blame^] | 169 | |
| 170 | int (*adv_pull_set)(struct mtk_pinctrl *hw, |
| 171 | const struct mtk_pin_desc *desc, bool pullup, |
| 172 | u32 arg); |
| 173 | int (*adv_pull_get)(struct mtk_pinctrl *hw, |
| 174 | const struct mtk_pin_desc *desc, bool pullup, |
| 175 | u32 *val); |
Sean Wang | a1a503a | 2018-09-08 19:07:17 +0800 | [diff] [blame] | 176 | }; |
| 177 | |
| 178 | struct mtk_pinctrl { |
| 179 | struct pinctrl_dev *pctrl; |
| 180 | void __iomem *base; |
| 181 | struct device *dev; |
| 182 | struct gpio_chip chip; |
| 183 | const struct mtk_pin_soc *soc; |
| 184 | struct mtk_eint *eint; |
| 185 | }; |
| 186 | |
| 187 | void mtk_rmw(struct mtk_pinctrl *pctl, u32 reg, u32 mask, u32 set); |
| 188 | |
| 189 | int mtk_hw_set_value(struct mtk_pinctrl *hw, int pin, int field, int value); |
| 190 | int mtk_hw_get_value(struct mtk_pinctrl *hw, int pin, int field, int *value); |
| 191 | |
Sean Wang | 85430152 | 2018-09-08 19:07:24 +0800 | [diff] [blame] | 192 | int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, |
| 193 | const struct mtk_pin_desc *desc); |
| 194 | int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, |
| 195 | const struct mtk_pin_desc *desc, int *res); |
| 196 | int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, |
| 197 | const struct mtk_pin_desc *desc, bool pullup); |
| 198 | int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, |
| 199 | const struct mtk_pin_desc *desc, bool pullup, |
| 200 | int *res); |
| 201 | |
Sean Wang | c283219 | 2018-09-08 19:07:22 +0800 | [diff] [blame] | 202 | int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, |
| 203 | const struct mtk_pin_desc *desc, u32 arg); |
| 204 | int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, |
| 205 | const struct mtk_pin_desc *desc, int *val); |
| 206 | |
Sean Wang | 3ad38a1 | 2018-09-08 19:07:23 +0800 | [diff] [blame] | 207 | int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, |
| 208 | const struct mtk_pin_desc *desc, u32 arg); |
| 209 | int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, |
| 210 | const struct mtk_pin_desc *desc, int *val); |
| 211 | |
Sean Wang | 0d7ca77 | 2018-09-08 19:07:25 +0800 | [diff] [blame^] | 212 | int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, |
| 213 | const struct mtk_pin_desc *desc, bool pullup, |
| 214 | u32 arg); |
| 215 | int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, |
| 216 | const struct mtk_pin_desc *desc, bool pullup, |
| 217 | u32 *val); |
| 218 | |
Sean Wang | a1a503a | 2018-09-08 19:07:17 +0800 | [diff] [blame] | 219 | #endif /* __PINCTRL_MTK_COMMON_V2_H */ |