| commit | fdd0dbd8a28612195dfbfb08c404ef5bcfa48e43 | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Wed Jun 03 10:36:39 2015 +0200 |
| committer | Simon Horman <horms+renesas@verge.net.au> | Fri Feb 19 14:52:23 2016 +0900 |
| tree | 553f9d04e8368197e6c5c8b49e573d51677bf942 | |
| parent | 8ffe93a5b2cb55d4da9c285d9277699bdb828b47 [diff] |
ARM: dts: r8a7793: Add L2 cache-controller node Add a device node for the L2 cache, and link the CPU node to it. The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as 64 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>