| commit | fa2d185f7518423ffcdba617ad09ff77ac51f198 | [log] [tgz] |
|---|---|---|
| author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | Wed Sep 09 22:13:28 2020 +0900 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Thu Sep 10 16:58:13 2020 +0200 |
| tree | 46996de71e38acfd680f67a9b4fb507a9c1b1e19 | |
| parent | c2ff0810934a925c9e6d96d7c400dee9bef8808e [diff] |
dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V3U (R8A779A0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599657211-17504-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>