| commit | f7ebf8874c2abb12be786fe73734ba47c87ff123 | [log] [tgz] |
|---|---|---|
| author | Joseph Lo <josephl@nvidia.com> | Fri Jan 04 11:06:50 2019 +0800 |
| committer | Thierry Reding <treding@nvidia.com> | Wed Feb 06 14:29:08 2019 +0100 |
| tree | 3f0ce27c8c84f918b81b4df7fc179b9f25f1db1d | |
| parent | 36541f0499fe02541de8edbcb05e6536104b11d2 [diff] |
clk: tegra: dfll: round down voltages based on alignment When generating the OPP table, the voltages are round down with the alignment from the regulator. The alignment should be applied for voltages look up as well. Based on the work of Penny Chiu <pchiu@nvidia.com>. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>