| commit | f4ca7a9260dfe700f2a16f0881825de625067515 | [log] [tgz] |
|---|---|---|
| author | Biao Huang <biao.huang@mediatek.com> | Fri May 24 14:26:09 2019 +0800 |
| committer | David S. Miller <davem@davemloft.net> | Sat May 25 11:02:31 2019 -0700 |
| tree | 5c28de197a879032f2fa9be19eb49c6eddad048c | |
| parent | 5e7f7fc538d894b2d9aa41876b8dcf35f5fe11e6 [diff] |
net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail
1. the frequency of csr clock is 66.5MHz, so the csr_clk value should
be 0 other than 5.
2. the csr_clk can be got from device tree, so remove initialization here.
Fixes: 9992f37e346b ("stmmac: dwmac-mediatek: add support for mt2712")
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>