| commit | f49b6aeb5c45dea3a1b6ee6a842599147dfd5929 | [log] [tgz] |
|---|---|---|
| author | Loic Poulain <loic.poulain@linaro.org> | Thu Nov 26 16:06:41 2020 +0100 |
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | Thu Jan 21 13:05:53 2021 +0530 |
| tree | 5b4991575ae1180a241988ff51f7062d2512947c | |
| parent | ec751369d6fbc9f84176e1530b11cbf387262b48 [diff] |
bus: mhi: Ensure correct ring update ordering with memory barrier The ring element data, though being part of coherent memory, still need to be performed before updating the ring context to point to this new element. That can be guaranteed with a memory barrier (dma_wmb). Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>