ARM: ux500: Enable PL310 Level 2 Cache Controller in Device Tree
This provides PL310 Level 2 Cache Controller Device Tree
support for all u8500 based devices.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index 614a471..ce3b56f 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -29,6 +29,14 @@
<0xa0410100 0x100>;
};
+ L2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0xa0412000 0x1000>;
+ interrupts = <0 13 4>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 7 0x4>;