| commit | eede7113aabd3f40f8d9c32b1690f2859fcb101a | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Mon Apr 20 15:10:43 2015 +0200 |
| committer | Thierry Reding <treding@nvidia.com> | Thu Apr 28 12:41:49 2016 +0200 |
| tree | ffa6885caeb0e7e1a1e1a64161a4082771cceedc | |
| parent | 98c4b3661b5aee0e583d17d6304f6489c0f41155 [diff] |
clk: tegra: dpaux and dpaux1 are fixed factor clocks The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have a gate bit in the peripheral clock registers. Signed-off-by: Thierry Reding <treding@nvidia.com>