| commit | eec26555ae9bf69da8bfe90cacdbc85d7a23391b | [log] [tgz] |
|---|---|---|
| author | Tony Lindgren <tony@atomide.com> | Mon May 27 04:51:54 2019 -0700 |
| committer | Tony Lindgren <tony@atomide.com> | Tue May 28 05:19:15 2019 -0700 |
| tree | 5bd8636931cff896b1ddd44f22c214fa52b868c3 | |
| parent | bd808f9a442301e493fe0bb3168774b4da7bb605 [diff] |
bus: ti-sysc: Enable interconnect target module autoidle bit on enable For interconnect target modules with autoidle bit wired, we need to manage it for enable and disable. Tested-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>