tree 163488134796b1dd5b835776572ec07c3e416fb5
parent 1a695a905c18548062509178b98bc91e67510864
author Thierry Reding <treding@nvidia.com> 1454689052 +0100
committer Thierry Reding <treding@nvidia.com> 1465567904 +0200

clk: tegra: Fixup post dividers on Tegra210

Commit 86c679a52294 ("clk: tegra: pll: Fix _pll_ramp_calc_pll logic and
_calc_dynamic_ramp_rate") changed the PLL divider computation logic to
consistently use P-divider values from tables as real dividers rather
than the hardware values. Unfortunately for some reason many of the
Tegra210 clocks didn't have their tables updated (most likely an over-
sight by me when applying the patches). This commit fixes them all up.

Cc: Jon Hunter <jonathanh@nvidia.com>
Cc: Rhyland Klein <rklein@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>