| commit | ec15c4d0d5d2e431169fbdf6c6bcf0c8ff71ef22 | [log] [tgz] |
|---|---|---|
| author | Ley Foon Tan <ley.foon.tan@intel.com> | Wed Apr 24 12:57:14 2019 +0800 |
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | Thu May 30 15:28:01 2019 +0100 |
| tree | bd01cf8a894bb339051716fd86ab5c14ff783be2 | |
| parent | a188339ca5a396acc588e5851ed7e19f66b0ebd9 [diff] |
PCI: altera: Allow building as module Altera PCIe Rootport IP is a soft IP and is only available after an FPGA image (whose design contains it) is programmed. Make driver modulable to support use cases when FPGA image is programmed after the kernel has booted, so that the driver can be loaded upon request. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>