tree 6c1eedad4943ec3ed06e689c911fa1d66d34ee4c
parent 92b59929825d67db575043a76651865d16873b36
author John David Anglin <dave.anglin@bell.net> 1372538532 -0400
committer Helge Deller <deller@gmx.de> 1373400562 +0200

parisc: Ensure volatile space register %sr1 is not clobbered

I still see the occasional random segv on rp3440.  Looking at one of
these (a code 15), it appeared the problem must be with the cache
handling of anonymous pages.  Reviewing this, I noticed that the space
register %sr1 might be being clobbered when we flush an anonymous page.

Register %sr1 is used for TLB purges in a couple of places.  These
purges are needed on PA8800 and PA8900 processors to ensure cache
consistency of flushed cache lines.

The solution here is simply to move the %sr1 load into the TLB lock
region needed to ensure that one purge executes at a time on SMP
systems.  This was already the case for one use.  After a few days of
operation, I haven't had a random segv on my rp3440.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
Cc: <stable@vger.kernel.org> # 3.10
Signed-off-by: Helge Deller <deller@gmx.de>