tree 17c61ab18ac405e8cfb52930787367f285e16f73
parent 6cfc8bc9ee66677fbd1b3331167d6f520e30b6fd
author Peter De Schrijver <pdeschrijver@nvidia.com> 1488292641 +0200
committer Thierry Reding <treding@nvidia.com> 1490015253 +0100

clk: tegra: Add super clock mux/divider

Add a super clock type which implements both mux and divider. This is
used for aclk.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>