tree 19890695e2499f3b07a1e3a9b434a0cecc9e6bb7
parent 42329854410e672b7ffeb391d284ad719efcc465
author Sowjanya Komatineni <skomatineni@nvidia.com> 1588645915 -0700
committer Thierry Reding <treding@nvidia.com> 1589316523 +0200

clk: tegra: Add Tegra210 CSI TPG clock gate

Tegra210 CSI hardware internally uses PLLD for internal test pattern
generator logic.

PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD
out to CSI during TPG mode.

This patch adds this CSI TPG clock gate to Tegra210 clock driver
to allow Tegra video driver to ungate CSI TPG clock during TPG mode
and gate during non TPG mode.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>