| commit | dc4e62d373f881cbf51513296a6db7806516a01a | [log] [tgz] |
|---|---|---|
| author | Jerome Brunet <jbrunet@baylibre.com> | Mon May 13 14:31:11 2019 +0200 |
| committer | Jerome Brunet <jbrunet@baylibre.com> | Mon May 20 12:18:55 2019 +0200 |
| tree | 188605959275fc3943f12417ec03e53506d79c18 | |
| parent | 8925dbd03bb29b1b0de30ac4e02c18faf8ddc9db [diff] |
clk: meson: axg: spread spectrum is on mpll2
After testing, it appears that the SSEN bit controls the spread
spectrum function on MPLL2, not MPLL0.
Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>