extcon: sm5502: Add support for SM5504
SM5504 is another MUIC from Silicon Mitus that is fairly similar
to SM5502. They seem to use the same register set, but:
- SM5504 has some additional bits in SM5502_REG_CONTROL
- SM5504 has a quite different set of interrupts
- SM5504 reports USB OTG as dev_type1 = BIT(0) instead of BIT(7)
Overall it's minor and we can support this by defining a separate
struct sm5502_type for SM5504.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
diff --git a/drivers/extcon/extcon-sm5502.h b/drivers/extcon/extcon-sm5502.h
index d187205..9c04315 100644
--- a/drivers/extcon/extcon-sm5502.h
+++ b/drivers/extcon/extcon-sm5502.h
@@ -89,6 +89,13 @@ enum sm5502_reg {
#define SM5502_REG_CONTROL_RAW_DATA_MASK (0x1 << SM5502_REG_CONTROL_RAW_DATA_SHIFT)
#define SM5502_REG_CONTROL_SW_OPEN_MASK (0x1 << SM5502_REG_CONTROL_SW_OPEN_SHIFT)
+#define SM5504_REG_CONTROL_CHGTYP_SHIFT 5
+#define SM5504_REG_CONTROL_USBCHDEN_SHIFT 6
+#define SM5504_REG_CONTROL_ADC_EN_SHIFT 7
+#define SM5504_REG_CONTROL_CHGTYP_MASK (0x1 << SM5504_REG_CONTROL_CHGTYP_SHIFT)
+#define SM5504_REG_CONTROL_USBCHDEN_MASK (0x1 << SM5504_REG_CONTROL_USBCHDEN_SHIFT)
+#define SM5504_REG_CONTROL_ADC_EN_MASK (0x1 << SM5504_REG_CONTROL_ADC_EN_SHIFT)
+
#define SM5502_REG_INTM1_ATTACH_SHIFT 0
#define SM5502_REG_INTM1_DETACH_SHIFT 1
#define SM5502_REG_INTM1_KP_SHIFT 2
@@ -119,6 +126,36 @@ enum sm5502_reg {
#define SM5502_REG_INTM2_STUCK_KEY_RCV_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT)
#define SM5502_REG_INTM2_MHL_MASK (0x1 << SM5502_REG_INTM2_MHL_SHIFT)
+#define SM5504_REG_INTM1_ATTACH_SHIFT 0
+#define SM5504_REG_INTM1_DETACH_SHIFT 1
+#define SM5504_REG_INTM1_CHG_DET_SHIFT 2
+#define SM5504_REG_INTM1_DCD_OUT_SHIFT 3
+#define SM5504_REG_INTM1_OVP_EVENT_SHIFT 4
+#define SM5504_REG_INTM1_CONNECT_SHIFT 5
+#define SM5504_REG_INTM1_ADC_CHG_SHIFT 6
+#define SM5504_REG_INTM1_ATTACH_MASK (0x1 << SM5504_REG_INTM1_ATTACH_SHIFT)
+#define SM5504_REG_INTM1_DETACH_MASK (0x1 << SM5504_REG_INTM1_DETACH_SHIFT)
+#define SM5504_REG_INTM1_CHG_DET_MASK (0x1 << SM5504_REG_INTM1_CHG_DET_SHIFT)
+#define SM5504_REG_INTM1_DCD_OUT_MASK (0x1 << SM5504_REG_INTM1_DCD_OUT_SHIFT)
+#define SM5504_REG_INTM1_OVP_EVENT_MASK (0x1 << SM5504_REG_INTM1_OVP_EVENT_SHIFT)
+#define SM5504_REG_INTM1_CONNECT_MASK (0x1 << SM5504_REG_INTM1_CONNECT_SHIFT)
+#define SM5504_REG_INTM1_ADC_CHG_MASK (0x1 << SM5504_REG_INTM1_ADC_CHG_SHIFT)
+
+#define SM5504_REG_INTM2_RID_CHG_SHIFT 0
+#define SM5504_REG_INTM2_UVLO_SHIFT 1
+#define SM5504_REG_INTM2_POR_SHIFT 2
+#define SM5504_REG_INTM2_OVP_FET_SHIFT 4
+#define SM5504_REG_INTM2_OCP_LATCH_SHIFT 5
+#define SM5504_REG_INTM2_OCP_EVENT_SHIFT 6
+#define SM5504_REG_INTM2_OVP_OCP_EVENT_SHIFT 7
+#define SM5504_REG_INTM2_RID_CHG_MASK (0x1 << SM5504_REG_INTM2_RID_CHG_SHIFT)
+#define SM5504_REG_INTM2_UVLO_MASK (0x1 << SM5504_REG_INTM2_UVLO_SHIFT)
+#define SM5504_REG_INTM2_POR_MASK (0x1 << SM5504_REG_INTM2_POR_SHIFT)
+#define SM5504_REG_INTM2_OVP_FET_MASK (0x1 << SM5504_REG_INTM2_OVP_FET_SHIFT)
+#define SM5504_REG_INTM2_OCP_LATCH_MASK (0x1 << SM5504_REG_INTM2_OCP_LATCH_SHIFT)
+#define SM5504_REG_INTM2_OCP_EVENT_MASK (0x1 << SM5504_REG_INTM2_OCP_EVENT_SHIFT)
+#define SM5504_REG_INTM2_OVP_OCP_EVENT_MASK (0x1 << SM5504_REG_INTM2_OVP_OCP_EVENT_SHIFT)
+
#define SM5502_REG_ADC_SHIFT 0
#define SM5502_REG_ADC_MASK (0x1f << SM5502_REG_ADC_SHIFT)
@@ -195,6 +232,9 @@ enum sm5502_reg {
#define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT)
#define SM5502_REG_DEV_TYPE1_USB_OTG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT)
+#define SM5504_REG_DEV_TYPE1_USB_OTG_SHIFT 0
+#define SM5504_REG_DEV_TYPE1_USB_OTG_MASK (0x1 << SM5504_REG_DEV_TYPE1_USB_OTG_SHIFT)
+
#define SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT 0
#define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT 1
#define SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT 2
@@ -273,4 +313,42 @@ enum sm5502_irq {
#define SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK BIT(4)
#define SM5502_IRQ_INT2_MHL_MASK BIT(5)
+/* SM5504 Interrupts */
+enum sm5504_irq {
+ /* INT1 */
+ SM5504_IRQ_INT1_ATTACH,
+ SM5504_IRQ_INT1_DETACH,
+ SM5504_IRQ_INT1_CHG_DET,
+ SM5504_IRQ_INT1_DCD_OUT,
+ SM5504_IRQ_INT1_OVP_EVENT,
+ SM5504_IRQ_INT1_CONNECT,
+ SM5504_IRQ_INT1_ADC_CHG,
+
+ /* INT2 */
+ SM5504_IRQ_INT2_RID_CHG,
+ SM5504_IRQ_INT2_UVLO,
+ SM5504_IRQ_INT2_POR,
+ SM5504_IRQ_INT2_OVP_FET,
+ SM5504_IRQ_INT2_OCP_LATCH,
+ SM5504_IRQ_INT2_OCP_EVENT,
+ SM5504_IRQ_INT2_OVP_OCP_EVENT,
+
+ SM5504_IRQ_NUM,
+};
+
+#define SM5504_IRQ_INT1_ATTACH_MASK BIT(0)
+#define SM5504_IRQ_INT1_DETACH_MASK BIT(1)
+#define SM5504_IRQ_INT1_CHG_DET_MASK BIT(2)
+#define SM5504_IRQ_INT1_DCD_OUT_MASK BIT(3)
+#define SM5504_IRQ_INT1_OVP_MASK BIT(4)
+#define SM5504_IRQ_INT1_CONNECT_MASK BIT(5)
+#define SM5504_IRQ_INT1_ADC_CHG_MASK BIT(6)
+#define SM5504_IRQ_INT2_RID_CHG_MASK BIT(0)
+#define SM5504_IRQ_INT2_UVLO_MASK BIT(1)
+#define SM5504_IRQ_INT2_POR_MASK BIT(2)
+#define SM5504_IRQ_INT2_OVP_FET_MASK BIT(4)
+#define SM5504_IRQ_INT2_OCP_LATCH_MASK BIT(5)
+#define SM5504_IRQ_INT2_OCP_EVENT_MASK BIT(6)
+#define SM5504_IRQ_INT2_OVP_OCP_EVENT_MASK BIT(7)
+
#endif /* __LINUX_EXTCON_SM5502_H */