| commit | d4eead50eb206b875f54f66cc0f6ec7d54122c28 | [log] [tgz] |
|---|---|---|
| author | Imre Deak <imre.deak@intel.com> | Tue Jul 09 17:05:26 2013 +0300 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Tue Jul 09 16:35:50 2013 +0200 |
| tree | f94f8acf87faffa3585bd8920a0f8bd72224d2dc | |
| parent | aaf8a5167291b65e9116cb8736d862965b57c13a [diff] |
drm/i915: fix lane bandwidth capping for DP 1.2 sinks DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which the driver will treat as an invalid value and use 1.62Gbps instead. Fix this by capping to 2.7Gbps for sinks reporting a 5.4Gbps max bw. Also add a warning for reserved values. v2: - allow only bw values explicitly listed in the DP standard (Daniel, Chris) Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>