tree 2d30d6656ef0d3fd57f78045830b9c21ae69a5ae
parent 21db403660d1433b8a02b26d5d4084921b857c40
author Palmer Dabbelt <palmer@sifive.com> 1511906777 -0800
committer Palmer Dabbelt <palmer@sifive.com> 1511906777 -0800

RISC-V: `sfence.vma` orderes the instruction cache

This is just a comment change, but it's one that bit me on the mailing
list.  It turns out that issuing a `sfence.vma` enforces instruction
cache ordering in addition to TLB ordering.  This isn't explicitly
called out in the ISA manual, but Andrew will be making that more clear
in a future revision.

CC: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>